Description

RECOMMENDATION: LONG Marvell (MRVL US) with 60-120%+ upside. Marvell is a clear AI beneficiary, consisting of multiple misunderstood, high-quality businesses that are only now starting to inflect strongly. These inflections will (i) drive aggressive DD%+ beats on 2025 and 2026 consensus numbers + (ii) modest beats in 2H24 + (iii) accelerate MRVL’s long-term EPS algo, leading to a significant AI-driven re-rating.

MRVL’s business includes numerous compressed, coiled springs in the way of: 1) custom AI chip (ASIC) ramps across numerous marquee customers (AMZN, GOOGL, MSFT, and 2 others) starting to ramp now that will aggressively accelerate in 2025-2026 + 2) new, transformative custom AI chip mandates will turn on in 2025-2026 (2-4 others that are not disclosed) + 3) an AI-driven networking acceleration that will occur in 2025 that bears are completely misunderstanding + 4) troughed non-AI end markets that will begin comping positive in 2H2024 / accelerate powerfully in 2025 + 5) take-out call options.

YTD, MRVL has materially lagged its chipmaking peers (YTD, MRVL has traded sideways, when AVGO is up ~+30% YTD, and NVDA ~+100%), making MRVL an interesting catch-up AI investment as it becomes a clear compute partner to hyperscaler customers. MRVL’s forthcoming inflections will put MRVL’s EPS algo on an AVGO-like long-term trajectory, allowing for investor capital to compound well above 30%+ p.a.

DESCRPTION:

• MRVL is a producer of semiconductor chips largely into the data center (~70% of Marvell’s business)
• Key businesses include producing 1) custom chips for large tech companies; 2) chips that facilitate the movement of data throughout the data center (#1 70%+ market share of DSPs); 3) chips that facilitate data movement in markets outside of data center that have troughed (networking, carrier, auto / industrial, and consumer)
• VIC member, “jso1123” provided an overview on the business in his 2/22/2024 write up, so please see his / her post for more information

THESIS 1: 100% of the leading, large tech companies (hyperscalers) are in the process of developing their own custom chips (custom ASICs) for AI and non-AI use cases. Designing advanced custom chips is an extremely complex process and so all of the hyperscalers are partnering with a design partner, either Marvell or Broadcom, for help. Marvell has won 2 of the largest hyperscalers’ AI chips (AMZN and MSFT) + key chips from Google + won 2-4 other key projects that are going to ramp in 2025-2026 and are either far undersized or neglected completely in consensus models

• Hyperscalers will all develop enormous custom chip programs: all of the large tech companies share the perspective that they must develop their own custom chips and that these custom chips will be integral drivers of their respective competitive advantages. Building custom compute offerings is a critical investment that each hyperscaler must make (in the long-term, there is no alternative)
• This decision to custom-design chips is extremely logical and mandated by physics:
  • 1) Historically, to make chips more efficient, they were made smaller (Moore’s Law). However, molecular limitations do not allow chips to be made substantially smaller anymore (Moore’s Law is breaking down). Therefore, to make chips more efficient, the chips must now be customized for their intended workloads (allowing the company to optimize the IP blocks, gates, and functionality to include only what is required for greater efficiency)
  • 2) It is logical for chips to be designed bespoke for their specific workloads given it is very inefficient for a single chip to be used across vastly different functionalities (e.g., it is not an efficient use of resources for the chip that assists Google with search / AI to also be designed to assist Amazon with e-commerce / AI, Meta with social networking / video-specific AI, ByteDance with video / AI, etc.)
• Hyperscalers need to partner with either MRVL or AVGO to design custom chips on the bleeding edge: custom designing chips on the bleeding edge is extremely complex, customers do not have the resources and IP to design these chips in-house, and so these large tech companies have elected to partner with the industry’s 2 leading, independent design partners, MRVL or AVGO
• There is clear empirical evidence to support this view given all the leading hyperscalers have selected design partners: Google, Meta, and Bytedance have elected to partner with Broadcom and Amazon, Microsoft, and 2-4 others have elected to partner with Marvell
• $60bn+ duopolistic market: all of these hyperscalers have aggressive custom chip ramps that our research shows will create a $60-80bn+ market in 3-5 years. MRVL and AVGO are the only companies with the IP / experience to facilitate the market on the bleeding edge in a duopolistic structure
• MRVL’s competitive position is wildly misunderstood by bears: bears look at MRVL’s custom ASIC business and see it is <1/10^th the size of AVGO’s and therefore think MRVL’s technology is a distant laggard to AVGO’s and MRVL is uninteresting. This is wrong. MRVL’s custom design offering is actually much closer to AVGO’s and in some instances is preferred to AVGO given model disparities
  • Bear’s think MRVL is materially worse than AVGO given MRVL is smaller: AVGO’s custom ASIC team will generate well over $10bn this year in revenue yet MRVL management is guiding for MRVL to do run rate $800mm exiting the year. This has given bears the view that MRVL materially lags AVGO
  • MRVL’s chip design team actually rival’s AVGO’s: MRVL’s custom design team was the gold standard for chip design for decades dating back to when the team was with IBM Microelectronics, this team was then acquired by Global Foundries and developed experience working directly alongside a foundry (rare experience developing physical IP given design teams typically do not work alongside foundries in today’s industry structure), Global Foundries then spun the team out into Avera Semi, and that team was then acquired by MRVL. MRVL has then gone on to get multiple AI chips across the finish line for hyperscalers that are ramping now. Throughout this process, MRVL’s team has secured decades of experience + IP, developed the ability to work alongside the fab and push to the bleeding edge nanometer at a rapid clip, and showed they can get AI ASICs across the finish line
  • MRVL’s team is often the preferred partner relative to AVGO for numerous reasons: (i) throughout decades of design experience, MRVL’s team developed leading IP (including physical design IP from its experience working alongside a foundry with Global Foundries and ARM IP from its acquisition of Cavium); (ii) MRVL’s go-to-market strategy allows MRVL to drop into the customer’s design team to work cooperatively alongside the hyperscaler’s R&D team, allowing for greater flexibility in design and a stronger transparency with the customer (AVGO demands tight design parameters, a clean IP handoff, and minimal interaction between design teams); and (iv) AVGO has earned a poor reputation among customers for price gauging, resulting in sporadic public blowups between AVGO and its customers (recently Google and Apple), while MRVL prices below AVGO, but maintains 50%+ gross margins
  • MRVL is smaller than AVGO given it is only now turning on revenue: when the MRVL team was a part of Global Foundries / Avera Semi, the team was directed to focus only on internal Global Foundries projects. It was only after MRVL acquired the team at the end of 2019 that MRVL management allowed the team to hunt for bleeding edge external business. This led to wins with AMZN, Google, MSFT, and 2-4 other large, undisclosed projects that will start ramping 2025-2026
  • MRVL’s custom chip revenue will start to compound aggressively: MRVL’s custom ASIC business will 20x+ in the next 2-3 years on the back of already disclosed wins, well in excess of consensus estimates, per our research based on chip maps, 3^rd party work, and CoWoS / supply chain data points
• MRVL’s announced wins are underappreciated, will drive beats in 2H24, and aggressive outperformance in 2025-2026: after 3+ years of design work, MRVL is now ramping AMZN’s AI accelerator (Trainium2), will start to ramp Amazon’s inference accelerator in 4Q24 (Inferentia3), and is now ramping Google’s CPU. CoWoS numbers (input for AI chips) + supply chain data points / readthroughs indicate MRVL’s 2024 ramp will be in excess of the guide and the custom ramp will 2x+ in 2025
• MRVL will ramp its largest customer, MSFT, in 2025-2026: MRVL recently won MSFT, which will be larger than all of AMZN’s training AI chip (Trainium2) + AMZN’s inference chip (Inferentia3) + Google CPU combined. The chip will be at a high ASP given the technology (3nm + HBM4 memory) and our research shows will ramp at an extraordinary aggressive clip as MSFT seeks to catch up to the other large tech competitors’ programs (Google, AMZN, Meta, etc.), which MSFT lags after MSFT missteps on their first custom chip (Maia 100), which MSFT attempted to complete in house (Maia 100 was cut to ~5k units)
• MRVL will ramp 2-4 additional large wins 2025-2026: there are 2-4 more undisclosed large wins that will start to ramp in 2025 and aggressively ramp in 2026-2027, none of which are in consensus models
  • In 2026 and beyond, our research also shows MRVL also has a shot at a piece of the Google TPU, but this is not at all necessary to make MRVL interesting, so we exclude it from our analyses
• EPS upside from ASICs is enormous: for reference, a single large hyperscaler win is $500mm-1bn+ / year. However, larger hyperscaler wins generate multi-billion $s (e.g., Google, which is currently the largest, will do ~$10bn with AVGO this year). We think there is a reasonable case in which custom ASICs do $3-4+ in EPS for MRVL in CY2026, which is the entirety of MRVL’s St estimates (currently custom ASIC’s contribution to MRVL’s EPS is relatively immaterial)

THESIS 2: MRVL’s “AI revenue” is partially driven by semis that facilitate the transmission of data within the data center (optical digital signal processors). This business is positioned to accelerate meaningfully and bears are dramatically misunderstanding the opportunity

• Background context: MRVL dominates the high-end market for optical digital signal processors (PAM-4 DSPs), which are critical to the transmission of data throughout the data center. In regard to what DSPs do, the fastest way to transmit data is via light (optical), but servers and switches throughout the data center communicate in electrical current rather than light. Therefore, data must be converted from light to electrical current. The process of converting data from light to current is completed through digital signal processors (DSP). MRVL dominates the high end of this market with 70%+ share and has maintained this share for the past 5+ years
• There will be a surge in DSP demand that bears are missing: each AI chip (XPU) requires a number of DSPs (2-4 DSPs per XPU depending on the architecture) via an implied attach rate. Throughout 2025, XPU and switch volume will surge as customers continue to ramp offerings (NVDA Blackwell ramp, Google custom ASIC, AMZN custom ASIC, AMZN generally moving infrastructure from 400 gig to 800 gig, long-anticipated AMD ramp, Meta custom ASIC, MSFT buildout, etc.). To put numbers around words, MSD mm switch ports will come online in 2024. This will rise from MSD to ~25mm in 2025. Bears believe there may be too many DSPs in the channel today, but are missing that the market is way undersupplied throughout 2025-2026+, even if MRVL ramps at max capacity and so MRVL is positioned to see an optical acceleration
• There is a forthcoming optical upgrade cycle that will lead to 40%+ ASP uplift for the next optical generation: AI use cases are dramatically increasing the amount of data that must be transmitted throughout the data center, increasing the required bandwidth of the data center’s networking. These higher bandwidth requirements are driving an upgrade cycle in the networking, moving the leading networking speed from 800 gigabytes / second to 1.6 terabyte / second starting later this year / early next year. MRVL is the only company that has a functional DSP at 1.6T and the next player that is taped out, but not yet functional, consumes 50% more power than MRVL. Importantly, ASPs for optics rise 40%+ from 800 gig to 1.6T
• There is a forthcoming optical acceleration for use cases between data centers: DSPs are also used to transmit data from one data center to another data center in a process called “data center interconnect” (DCI). This market will accelerate meaningfully in 2025 and 2026 given (i) there is a step change in the volume of data centers that are being developed and (ii) much of these data centers are undersized / reginal in nature given limited land availability, and therefore the data centers have to be connected to other data centers via DCI (select hyperscalers have alluded to 100%+ growth in their DCI spend in 2025-2026). This DCI process requires a highly complicated “coherent DSP” and MRVL is one of the few companies that can provide this technology
• Bears believe MRVL will lose DSP share with NVDA, but are missing key mitigating variables:
  • There are enormous executional hurdles to take share from MRVL: MRVL is currently the only player with a 1.6T DSP, but there is another player that is taped out at 1.6T, but the DSP is not ready and consumes 50% more power than MRVL. Simultaneously, MRVL has consistently seen DSP competition by some of the strongest players in the industry (AVGO and Mellanox / NVDA) for 5+ years and despite this competition, MRVL has been able to maintain its 70%+ share on the bleeding edge. Bears are expecting significant share shift away from MRVL without appreciating the executional challenge of taking share from MRVL
  • In the event of a competitive offering, MRVL’s DSP business is far more diversified than bears believe: MRVL’s optical business is well diversified among customers. Only ~50% of MRVL’s optical business is AI-driven (exposed to share loss at the bleeding edge); of that 50% AI-exposed business, some portion is data center interconnect that is insulated from competitive pressure (likely 20-40% of AI optics is DCI, and rising), so 30-40% of optics is AI PAM-4 DSP exposed to competitive pressure; of the 30-40% exposed to PAM-4 AI, 3^rd parties estimate 52% of 2024 800 gig optics is NVDA-related and the remainder is other players, so only 15-20% of MRVL’s optics business would be exposed to competitive pressure; of the 15-20% of the optics that is AI, PAM-4 DSP, and NVDA, the end hyperscaler often spec’s in the DSP, so only some portion of the 15-20% will be subject to share loss from NVDA (hyperscalers will not want to use a DSP that consumes 50% more power); and of the subset of the 15-20% of the optical business that is exposed, it would take significant time to lose share since NVDA has 40+ variations that use DSPs and they therefore cannot be converted over at once. Net / net, likely only MSD% of the optical business is exposed to competitive pressure at the bleeding edge and that business is only at risk if significant executional hurdles are overcome (see above on MRVL staying ahead of the competition for 5+ years)
  • Natural offsets to potential share loss via unit economics: in the event of share loss, there are natural offsets given MRVL will see 40%+ ASP increase when they move to 1.6T and a 4-5x+ the volume of switch ports in 2025 relative to 2024
• Management has aggressively sandbagged the 2025 and 2026 AI guide: management has historically miscommunicated around the guide and so has explicitly elected to guide conservatively in the mid- / long-term (e.g., there was an incident earlier in the year when management prematurely spoke to custom ASIC growth that is only now showing up in numbers). Given these missteps, management is guiding for CY2025 AI revenue to exceed $2.5bn, which they have since indicated is a floor and we believe is far too conservative (will be beat by $1bn+ for CY2025 and well over $1bn in CY2026)

THESIS 3: non-AI business is bouncing along the bottom and will start to comp positively sequentially / accelerate throughout 2025

• Non-AI businesses are troughed: Marvell’s non-AI businesses (networking, carrier, storage, auto / industrial, consumer, etc.) are troughed and are starting to comp positive. Consensus numbers are likely in the right place and an investor will not be burned being exposed to these end markets

NEED-TO-BELIEVE MATH:

• Near-term beats: AMZN Trainium2 and Inferentia3 ramps this year, allowing for modest 2H24 beats / guides above consensus and throughout 2025-2026 DD%+ outperformance relative to St; 2025-2027 numbers are far too low once MSFT turns on along with 2-4 other programs that are not yet included in sell side models
• Valuation: the stock has historically traded for 30-50x St fwd. adj. EPS. Given end markets are troughed, the multiple has climbed north of 30x, but we think in a normalized environment a 30-35x+ multiple is appropriate (supported by DCF)
• Base case returns: $110 stock = 30x EPS of $3.70 for 60-70%+ upside; EPS is returned when we haircut all custom ASIC programs to low end of CoWoS implied range in the way of volume and ASPs and exclude all mandates that have not been announced
• Upside case: $150 stock = 30x EPS of $5 for 120%+ upside; base case assumptions around volume / ASPs + give partial credit for some but not all additional programs + once custom ASIC momentum becomes clear, people can look out further and apply a 30x multiple on ~$5 of EPS = $150 stock
• Downside case returns: stock trades down into $55 territory with AI factor sell off (occurring now) for mid-teens % downside

Catalyst

• Modest beats on 2H24 and DD%+ substantial beats on 2025-2026: modest beats / raises in 2H24 and then aggressive beats in 2025-2026 as shows completely redefined EPS growth algo
• Short squeeze as pair trading L/Ss get stuck: semis long / short investors have struggled to find attractive semis short candidates + AVGO (MRVL’s closest competitor) is one of the most crowded hedge fund LONGs in the semis space. This has pushed MRVL short interest north of 5% for a ~$60bn market cap name. As MRVL posts beats / raises, shorts focused on AVGO will get stuck relative to cost bases and potentially eventually squeeze
• Better appreciation for MRVL’s custom ASIC strength as programs ramp + show path to AVGO-like custom ASIC ramp
• Take-out upside: MRVL could be a viable takeout target for other chipmakers including AMD / Qualcomm. We do not think this is a base case outcome, but MRVL would be a logical target by providing industry-leading custom design talent + IP, enabling entry into its non-AI markets, offering custom design relationships with 4-5 key hyperscalers, offering networking components for another partner to create a single integrated network system, etc.