Description

Overview

Note that a discussion of Cadence Design Systems, Inc. (ticker: CDNS) requires a fair bit of technical jargon, so we have included a glossary as an Appendix with all acronyms and technical terms we use throughout the document. 

Cadence is one of the most important companies that no one has ever heard of. The company provides software, hardware, services, and reusable IC design blocks for semiconductor customers to design, configure, analyze, and verify ICs, and for systems companies to design, simulate, and verify electro-thermal and physical functionality of their ICs, PCBs, and systems products. Through these products and services, Cadence helps customers to optimize performance, minimize power consumption, shorten time to market, improve engineering productivity and reduce design, development, and manufacturing costs.

Cadence’s core competency is in computational software (computer science plus math), where they think they are the best in the world. They offer mission critical products and services – the software and hardware needed to design and test chips and electronic systems – that are low-cost relative to the value they provide.

Cadence boasts a strong competitive advantage centered in predictable and largely contractually recurring revenues, a stable oligopoly industry structure with scale, outstanding management, a pristine balance sheet, excellent financial returns, and strong growth prospects. Cadence is a broad-based play on the R&D expenditures of semiconductor design and manufacturing companies. It trades at a reasonable price relative to its prospects and quality and affords investors an attractive risk-adjusted return profile.

Cadence is a great way to play secular growth in AI and chips more broadly.

Note that Cadence has a December fiscal yearend. All references to LTM are to the 12-month period ending September 2023, unless otherwise noted. 

Note that we deduct stock-based compensation as a regular expense in all our profit calculations. Other than including stock-based compensation, we accept all of management’s other income statement adjustments as appropriate. 

The Business

Cadence is largely a “picks and shovels” services provider to designers of all things electronic. The company creates software and hardware to help customers develop electronic products, including ICs, SoCs, devices, and systems. In essence, they are helping customers create a blueprint for a chip, with its billions of microscopic transistors. Cadence then tests and verifies the functionality of those designs, both at the chip and system level. 

Cadence addresses customer needs for better performance, lower power consumption, shorter time to bring their products to market, better engineering productivity, and lower costs (design, development, and manufacturing). Cadence sells software, hardware, its own reusable IP chip design blocks, and related services. 

Before getting into the business, it’s worth taking a moment to go through the process of making a chip. Chip designers (i.e., Nvidia, Tesla, or Apple) will gather a group of engineers to begin working on a new design (a “design start”). They’ll incorporate some existing IP for processes that do not need to be reinvented (like the ability to charge the battery through a USB). They will license this IP from third parties (i.e., Arm, Synopsys, or Cadence) who have developed and proven out the technology. They will use EDA software (from Cadence or Synopsys) to design the chip and optimize for the characteristics it seeks (PPA, yield, heat, etc.). They will simulate the chip both on software and on hardware (from Cadence or Synopsys) to verify functionality at many stages along the way. They’ll partner with foundries (i.e., TSMC or Samsung) to ensure the manufacturing process will work as planned. They’ll then “tape out” the design for a first silicon manufacturing run, including creating a photomask (kind of like a stencil for the chip) and give that to the foundry. Then the foundry produces the chips in volume to be incorporated into electronic systems (which are typically built by system integrators, like Flex or Hon Hai/Foxconn). Cadence and its closest competitor, Synopsys, can both offer what’s called “full flow,” which means a customer can complete the entire chip design process using Cadence or Synopsys. 

Cadence has two main customer groups: chip designers and system designers: 

• Chip designers (~55% of revenue): Chip designers create computer chips. Examples include companies like Nvidia, Broadcom, Arm, and Analog Devices (some of whom also design systems). These companies develop ICs and related subcategories like processors, SoCs, AI, memory, analog, digital, and other types of chips. Chip customers use Cadence’s tools to design, configure, analyze, and verify the functionality of their ICs. All the top 20 semiconductor companies use Cadence’s digital software, and half of them use Cadence’s Cerebrus AI solution. 

• System designers (~45% of revenue): System designers create mobile phones, laptop and desktop computers, gaming systems, automobiles and the ADAS needed for autonomous driving, servers, cloud data center infrastructure, AI systems, aerospace and defense, medical equipment, and networking products, among other things. Examples would be firms like Apple, Meta, Dell, and Tesla (some of whom also design chips). These companies develop or purchase the sub-components for their products, including PCBs, ICs, and software. System designers use Cadence’s tools to design, simulate, and verify the electro-thermal and physical functionality of their ICs, PCBs, and systems products. This includes both the silicon (internally developed chips) and non-silicon (the holistic systems themselves) revenues coming from the systems companies. The non-silicon systems area is smaller, newer, higher margin, and grows faster for Cadence than its other business lines.

Historically, Cadence played in the EDA industry. Over the last decade or so, however, Cadence has broadened its reach beyond EDA and now reports revenue in five buckets (we have included CDNS’s description of these segments in an Appendix): 

• Custom IC Design and Simulation (21% of LTM revenue): customers license Cadence’s software to create schematic and physical representations of circuits down to the transistor level for analog, mixed signal, custom digital, memory, and RF designs. They then use tools optimized for each type of design to verify functionality at various points in the design process, including design capture, simulation, IC layout, and prep for manufacturing. Cadence has verification tools for the chip, package, and PCB. Among some of their more advanced solutions, Cadence offers products for three-dimensional transistors (FinFETs, GAA) and multi-patterning. 

• Digital Design and Signoff (27% of LTM revenue): customers license Cadence’s software to create logical representations of a digital circuit or an IC. They then use Cadence tools to verify the design is correct prior to implementation. Once verified, customers use other Cadence tools to implement the design representation or convert it to a format ready for silicon manufacturing. 

• Functional Verification (28% of LTM revenue): customers use these products to verify that their designs for circuitry or software are consistent with their functional specification. Cadence’s EDA tools simulate the design environment so that customers can see the tradeoffs in different factors like power and performance. They can then iterate until they have optimized the design for whatever constraints they have to manage. Recently, EDA companies have been using AI to help in this design optimization, which is becoming more important as the number of design parameters proliferates. Verification takes place throughout the design process, with a goal to identify as many potential functional problems as possible before manufacturing. Errors in the completed project can be extremely costly both in terms of dollars and time, so customers will go to great lengths to surface them early. Cadence offers different verification tools for each stage of the design process, and in total verification can take up to 70% of the total time to design a chip (per Morgan Stanley). Most of Cadence’s hardware sales are in this segment.

• IP (11% of LTM revenue): customers license Cadence’s internally developed and verified chip design blocks to integrate into their own ICs on a non-exclusive basis. By using Cadence’s pre-designed functional blocks, customers can accelerate their own product development processes and reduce the risk of errors. Cadence’s most popular IP include configurable DSPs, vertically targeted subsystems for AI, audio/voice, baseband and vision/imaging, controllers and physical interfaces for standard protocols, analog IP, high speed SerDes, PCI, and USB. They also offer verification IP. 

• SD&A (13% of LTM revenue): customers use Cadence’s offerings to develop systems (rather than just chips), including PCBs and advanced IC packages, and to analyze properties for these systems, including electromagnetic, electro-thermal, CFD, and other multiphysics effects (aerodynamics, hydrodynamics, propulsion, turbomachinery, heat transfer, combustion). The speed and proximity of signals on silicon (through packages on to boards, and through connectors and cables) exposes these electrical communications to various kinds of interference, like heat and electromagnetic radiation. Cadence’s tools can analyze and simulate these products to ensure they work as designed. 

Cadence typically licenses their products to customers for finite terms, generally for three years plus add-ons purchased intermittently. As the add-ons attach with a co-terminus basis, the weighted average contract term is around 2.5 years. EDA is sold almost entirely on a subscription basis, typically per seat. 

Cadence also sells or leases emulation and prototyping hardware. Emulation hardware is used to emulate a chip before it’s manufactured, giving customers the ability to run software on top of it, run tests, boot Windows or Android or run an AI stack, all before the chip goes to manufacturing. Emulation is an important and required process in chip design. Hardware sales, like software sales, tend to be tied to the number and size of customer designs.

Cadence has about 10k employees, with around 80% being engineers either in R&D or in the field. The company is based in San Jose, CA.

Cadence competes primarily with Synopsys in EDA. Siemens, which purchased EDA competitor Mentor Graphics in 2017 for $4.5 billion, is also a meaningful #3. Ansys is a more distant #4 in EDA, but is a major competitor in SD&A. Several upstart Chinese competitors are also trying to get a foothold in EDA, though with limited success so far.

Management

CEO Anirudh Devgan has been with Cadence since 2012, having come up through the R&D groups before being made President in late 2017 and CEO in December 2021. He joined Cadence from a competitor called Magma Design, where he was general manager of the Custom Business Design Unit, when it was acquired by Synopsys. Devgan received his B.Tech in electrical engineering from the Indian Institute of Technology in Delhi, and an M.S. and Ph.D. in electrical and computer engineering from Carnegie Mellon. Given the prevalence of engineers in the firm, it is important that the CEO has a strong background in engineering and computer science.

Devgan is not just well-educated and highly intelligent. He is methodical, thoughtful, purposeful, concise, and grounded. He is only 54 years old, and only a couple of years into the role, so we expect him to be there a long time. The CFO John Wall credits him with dramatically improving Cadence’s digital EDA capabilities to compete with Synopsys prior to his becoming CEO. This required making a product that wasn’t just good, but much better, to induce customers to switch. Devgan overhauled the product entirely, and his playbook became the foundation for Cadence’s more recent entry into SD&A. 

Devgan took over the helm from Lip-Bu Tan, who ran Cadence from 2009 to late 2021. Tan did wonderful things for Cadence. Prior to Tan taking the reins, Cadence was really struggling. The company massively underpriced the product, had unfocused management, and engaged in self-destructive industry practices including poor salesforce incentives. The onset of the great financial crisis pushed Cadence close to the brink. In 2009 and the ensuing few years, Tan came in and overhauled management, made a prescient move into a subscription pricing model founded on value-based pricing, greenlit Devgan to invest aggressively into digital EDA, conducted intelligent M&A, and later promoted Wall to CFO. He turned the company around in a major way and set Cadence on a great path. 

Wall himself deserves mentioning too. He started with the company 26 years ago and became CFO in 2017 (which was around when he started working closely with then President Devgan). At that time, growth was decelerating, and incremental margins were too low. He set the bar for margins much higher and took a close look at R&D, where most of the company’s investment is and was made. He found that roughly two-thirds of engineering time was spent on maintaining existing products while only one-third was on new products. Using internal data, he determined that the company was rushing products out the door before they were ready and then spending too much time working on bugs and fixes. His suggestion was to slow down the pace of introductions and focus energy on building new products right before pushing them out to customers. He also made engineers compete for investment dollars. Per Wall in August 2023, “They're dangerous now. They come looking for investment dollars, and they're showing us the press release, what the press release will look like. If you give me the dollars to do this. But I think they're much better at focusing. Like -- thinking like an investor, thinking like an owner and choosing projects or allocating the investment dollars to projects that they think will generate a return for investment. … I do a general allocation, and then I tend to tax all of the R&D groups. If you're doing the same thing as you did last year, I expect you to do it more efficiently. So we take 2% or 3% off of them, create an investment pool for Anirudh to allocate to new projects. And then we just encourage the teams to compete for those and try to think like owners in the efforts that they take on.” Through these efforts, Wall has flipped the old math, with most engineering time now spent on new products. He has given other examples too, like how he improved value selling among the sales teams. He also considers engineers to be the scarce resource, so he focuses a great deal on productivity to ensure the company is using its engineers’ time wisely (see Cadence vs. Synopsys section below). In general, Wall has been a data-driven leader who understands incentives, and he’s overseen a dramatic improvement in margins. The results speak for themselves (see Financial Results section below). 

He’s also been thoughtful in how he goes about allocating capital to share buybacks. He targets using 50% of free cash flow to offset dilution from stock comp and to reduce the share count. Here is Wall on how he thinks about it: “When I'm looking at things like our buyback policy for repurchasing shares, I'm always looking at the net present value of future cash flows. So we do this model, it kind of looks out a couple of decades to see what net present value, future cash flows look like. And just as an exercise, I wanted to look at what does it look like if we didn't have to chase Moore's Law. If Moore's Law slows down and a growth company turns it -- morphs into a value company over time. Well, then you take your 35% that you're spending in R&D would probably decline to something like more normal, like a 5% over time. But when you do that, it's quite interesting. Multiples come down, but the cash flow generation and the profit generation more than makes up for it and the near term, the time that you're able to collect that cash, you end up with pretty similar valuations, whether Moore's Law continues on indefinitely or whether Moore's Law slows down over the next 20 years.” 

Turning to the current strategy (introduced in 2019), management pursues what it calls “Intelligent System Design,” which centers on the merger of traditional EDA with system level design and AI: 

The main objective of the design excellence approach is to enable design teams to manage increasing complexity and verification throughput for analog, digital, and mixed signal chips without commensurately increasing the team size or extending the project schedule, while also reducing technical risks. This is the core EDA and IP businesses. 

From there they are growing into two new areas. The system innovation strategic area captures Cadence’s expansion into total system capabilities, including system design, simulation (including electromagnetic, electro-thermal, and other multiphysics analysis needed to optimize total system performance), as well as advanced packaging. Pervasive intelligence is required at every step of the design, grounded in computational engineering (Cadence’s core competency). They must optimize systems, hardware, and software simultaneously and in coherent fashion. This strategic area captures the ability to provide solutions and services to develop AI-enhanced systems, including using ML and deep learning capabilities to make IP and tools more automated and produce optimized results faster. AI can be helpful in determining optimal layouts (to increase manufacturing yield or improve performance), or to improve energy efficiency (reducing the distance data needs to travel or the resistance and capacitance of moving that data). For instance, Morgan Stanley estimates that ML algorithms reduce the number of design simulations needed from millions without ML to a few thousand with it.  

Management historically pursued smaller bolt-on acquisitions to round out technology offerings or establish a foothold in a new adjacency. For instance, in 2022 they bought OpenEye, which provides computational molecular modeling and simulation software used by pharma and biotech companies for drug discovery. That same year they bought Future Facilities, which provides electronics cooling analysis and energy performance optimization solutions for data center design and operations using physics-based 3D digital twins. 

Management has carefully created a culture around its engineering competency. Roughly 60% of their total employee base are R&D engineers and another 20% are field engineers. The CFO talks to a culture steeped in “servant leadership,” as the company was originally organized “by engineers, for engineers” to help in the design process as customers chased Moore’s Law. They also manage the business as a “compounder” (their term), with a long-term strategy built around high return investments meant to produce strong compounded returns for shareholders over many years.  

Business Quality

Cadence is an outstanding business that sports many attractive characteristics. 

Highly stable revenues.

Management considers roughly 85-90% of revenues to be “recurring,” which includes software arrangements, services, royalties, maintenance on IP licenses and hardware, and operating leases of hardware. The remaining 10-15% relates to sales of emulation and prototyping hardware and individual IP licenses, which can be a bit lumpier, but also tends to largely track software sales.

Their contracts average around three years in duration, so most of the coming year’s revenue is known and in backlog at the beginning of the year. Furthermore, absent companies going bankrupt, the amount of revenue that is at risk each quarter is small (on average, about 1/12 of total annual revenue) given the contractual agreements with customers. As it takes two years to design a chip, and new designs represent the future for customers’ businesses, the risk of attrition is low. Wall has said they have something like 99.9% renewal rates, other than customers that are acquired or go bankrupt. Canceling a contract puts the customer at the end of the cue, effectively implementing a two year pause on tech innovation. A CTO would be committing career suicide by doing that. Therefore, even in a period of macro weakness, revenue streams at Cadence should be stable. Wall also said it’s exceptionally rare for a renewal to be at a lower value than the expiring contract.

In addition, there’s a component of customer stickiness due to switching costs, as it is difficult for customers to change providers for this type of complex software that is imbedded in customer processes. The sales cycle, which is 3 to 6 months, speaks to this stickiness, as do the high levels of customer retention. 

Cadence provides a mission critical service (EDA and SD&A) in a mission critical industry (semiconductors and electronics systems) that represents a great value within the total design project cost for customers. 

Let’s look at EDA and SD&A first. EDA is a necessary and important part of the design process for a chip. Without EDA software, technology companies couldn’t build these complex masterpieces of modern science. Similar comments could be made about SD&A, as it is critical to optimize and verify performance and other attributes of electronic systems. Engineers in customers’ R&D labs work with Cadence’s software tools all day, every day.

Next let’s look at the industry’s importance. It goes without saying that semiconductors and electronic systems play a massive role in today’s modern society, including:

• Aerospace and defense

• AI

• AR

• Automotive (including ADAS)

• Communications (including 5G networks)

• Edge computing

• Gaming

• Healthcare (including drug discovery, proteomics, and genome sequencing)

• Hyperscale computing / data center infrastructure

• IoT

• Industrial equipment (including factory automation and 3D printing)

• Mobile devices (smartphones, watches/wearables, tablets)

• Networking

• Omniverse / digital twins

• PCs

• Speakers

• Televisions

• Transportation

• VR

It’s not hyperbole to say that the global economy rests on the shoulders of this industry.

Finally, let’s look at the value equation for Cadence’s services. Morgan Stanley estimates that it costs $100 million to $1 billion to design a state-of-the-art processor, with several hundred engineers working for 12-18 months:  

Improving efficiency for this design process can lead to major savings. For example, if an advanced chip costs ~$500 million to design, and Cadence’s tools can eliminate the need for 10% of the research staff for the project, that could lead to $50 million in savings. Furthermore, designing the chip well the first time avoids extremely expensive mistakes down the line. For instance, just producing a photomask costs around $10 million (per Colossus Business Breakdowns), and the cost of producing finished chips that need to be thrown out could dwarf that figure.

Another way to look at it is from a macro level. Cadence has said that about 10% of customers’ R&D goes to EDA, and industry sources show R&D spend by chip companies in the U.S. alone was $59 billion in 2022 (per SIA). The company and other third parties peg the EDA market at around $10 billion globally, which implies global R&D spend on chips is perhaps around $100 billion. In comparison to the $574 billion in total global semiconductor sales in 2022 (per SIA), R&D would therefore work out to around 17%, while EDA itself would be less than 2%. That is a tiny amount for the value it provides, and that doesn’t even account for the trillions of dollars spent on the products that use those chips (the cloud, smartphones, PCs, etc.). 

Demand for EDA and SD&A stems from the combination of increasing complexity in electronics and customer investment in new designs and products. Said differently, demand comes from technological progress and investment in R&D. These tend to be non-cyclical areas of spending, as R&D is one of the last areas that customers will want to cut absent a draconian downturn. Here is some industry data (per SIA for the U.S. only, which can be a proxy for the global market): 

Furthermore, demand is widespread, impacted by almost every industry on the planet, as more and more companies incorporate technological solutions in their businesses and products. In the 2000s, chips mainly went into PCs. In the 2010s, they mainly went into mobile devices. Now, they go into just about everything. As Devgan said, “So almost all semiconductors in the world will require some form of our software to do the design and same thing, increasingly, for electronic systems. So this is all geographies, all verticals.” This widespread demand creates a diversification effect that smooths out the impact of individual industry cycles.

Ultimately, the proof of Cadence’s revenue stability is in the pudding. The following chart shows Cadence’s revenue going back to 2010 (per Macrotrends): 

We can see that while growth does move up and down a bit on a quarterly basis (bottom chart), it has been positive every quarter and is quite stable when viewed on an annual basis (top chart). These results came despite suffering through a number of chip cycles during this period, including the aftermath of the great financial crisis, the industrial recession of 2015/2016, the Chinese trade wars, and the Covid pandemic. 

Stable oligopoly industry structure with scale.

Cadence competes primarily with Synopsys and Siemens (Mentor Graphics), and to a lesser extent with Ansys and regional competitors mainly in China (like Huada Empyrean Avatar, Xpeedic, X-EPIC, Primarius Technologies, Univista, and Giga-DA). TrendForce indicates a 30% share for Cadence vs. 32% for Synopsys, 13% for Siemens/Mentor Graphics, and 25% for all the others combined as of 2021. They put the global EDA market size at $10.7 billion in 2022. Cadence itself claims to have an 18% share of a $10 billion EDA market and a 9% share of a $9 billion simulation market, though they arguably have an incentive to show a bigger market and smaller share. Cadence appears to have been a share gainer, as one data source on SeekingAlpha showed them gaining 500 bps of share from 2017 to 2022, as did Synopsys, while the other players lost share. Within certain business lines, Cadence has a much higher share than the overall figures show. For instance, they believe they have about 80% of the market for analog / custom IC EDA, and about 80% of the market for advanced packaging. They claim to have roughly 50% share for digital EDA, Synopsys’s historical stronghold. In real terms, however, Cadence and Synopsys are not duking it out to displace each other. Almost every chip designer of any significance uses products from both companies. 

New entrants would find it difficult to compete due to the requirement for intense engineering knowledge (roughly 80% of Cadence’s employees are engineers) and the barrier created by four decades of data analysis and software development. Cadence invests 35-40% of its revenues in R&D, a mind-bogglingly huge investment that would be hard for an upstart to replicate.

For instance, AI effectiveness depends on having reams of data, which an upstart would not have. Management is exploiting its advantage to harness AI for both internal and external purposes. They are using their JedAI big data analytics platform, which contains Cadence’s massive amounts of design and verification data to bring forward learnings for future designs. Customers need to run lots of options and changes through an iterative process to design a high-quality chip or system. AI can help with this, and they claim that tools like Cadence’s Cerebrus can improve productivity by 5-10x (in part by automating repetitive tasks and producing new ideas) and PPA by 10-20%. This is a massive improvement. For instance, the PPA gain approximates what designers achieve by moving from one node to the next (like 7-nm to 5-nm). AI tools require a bigger investment on the part of customers, so Cadence should see an uptick in revenue from this growing trend. 

Core competency in computational software.

Management frequently talks to their core competency in computational software, which they describe as “computer science plus math.” As the CFO says, applying computational software to silicon is EDA. Applying computational software to designing a phone, a plane, or a car is system design and analysis. As mentioned, this expertise and decades of accumulated knowledge create a formidable competitive barrier. Management talks about employing Cadence’s computational software capabilities to do both traditional “outside in” science – the observable math between inputs (X) and outputs (Y) – and “inside out” science – the physics, chemistry, or biology that are inherent properties of the system. Both lend themselves to heavy math and computer science, and both require significant simulation. Management looks for areas where the math and algorithms needed to do great analytical work are extremely complicated. For instance, simulating a cutting-edge chip entails analyzing perhaps 50 or 100 billion variables as there are billions of transistors. 

This core competency lends itself to many new and growing markets, where computer science and math play big roles. For instance, AI is computational software, with training and inference based on matrix multiplication or conjugate gradient concepts. No one else seems to be going after the combination of EDA and SD&A the way Cadence is.

Growth

Management highlights three main areas of growth: (1) semiconductor companies increasing design work, (2) system companies designing their own silicon (semi companies designing their own systems is also a growth area), and (3) Cadence expanding its addressable market by moving into SD&A.

More design work.

Management expects core EDA to be a high single digit to low double-digit revenue growth industry over the medium term. TrendForce’s expectation was for 14% growth in 2023 and 11% growth in 2024, consistent with management’s outlook. Morgan Stanley’s expectation is for a 9% CAGR through 2030. 

We’ve already mentioned the drivers of semiconductor demand in the discussion around business quality: increasing complexity in electronics and technology more broadly, and customer investment in R&D. The two go hand in hand, as the increasing complexity is leading to higher investment in R&D. When a customer like Apple moves from the 5-nm node to the 3-nm mode, for instance, the design gets exponentially more complicated and expensive, requiring more people and tools to build the chips. We can see this in many trends. For example, whereas packages used to have just one chip, now they may have multiple chips, arranged side-by-side or stacked on top of each other (called 3D-IC). This is necessary because the nodes have gotten so small that it has become exceedingly difficult to shrink them further due to physical constraints like the size of a wavelength of light (what some call the end of “Moore’s Law”). 

Moore’s Law isn’t dead yet. It will probably go for at least another decade as design work is currently being done on 3-nm, 2-nm, 1.4-nm, and 1-nm nodes. Every move down a node tends to double the number of transistors, so the sheer number of transistors on a chip has grown dramatically. The current advanced node chips have over 100 billion transistors, and management expects that to grow to 1 trillion by 2030, a 10x increase. Including the software on top, the design complexity might increase by a factor of 20-40x over the next 5 to 7 years due to the nonlinear relationship. A doubling of transistors will lead to exponential growth in state spaces and gate count, requiring more simulators and emulators. Furthermore, chip designers will find it impossible to hire enough engineers to handle 20-40x the amount of work, requiring them to use AI tools like the ones Cadence already offers. [Management says that only 10% of customer R&D spend is going to automation, while 90% goes to people, up from 8%/92% a few years ago. Cadence believes that over time more spend will shift to automation / AI to lessen the need for people.] As the CFO says, “The human population isn’t growing fast enough, even if more of them become engineers, to keep up with the pace of growth and complexity” of technology. This is another factor leading to Cadence outgrowing the industry.

Systems companies designing their own silicon.

Cadence management moved aggressively to expand the company’s systems business over the last few years, having grown from 40% of revenue in 2018 to 45% today. This follows recent initiatives by system companies to make their own silicon. The trend started with the phone companies (Apple) but has moved into other areas like autos (Tesla) and data centers (Google, Microsoft, Amazon). This has been a major change in the industry as systems companies realized that designing their own chips could lead to meaningful differentiation. Apple was one of the early movers in 2008, and Amazon made a big move with its acquisition of Annapurna Labs in 2015, which they’ve grown by a factor of 10 or more. Google is another. Almost all of today’s largest companies design some of their own chips, as are many smaller companies. Given their lack of history in the area, systems companies need to develop their chip design capabilities from scratch. This is creating a bigger bucket of R&D funds from which Cadence can get paid.

Expanding TAM into SD&A.

Another considerable area of growth that piggybacks on the relationship with systems companies is Cadence’s move from EDA into broader SD&A. This initiative began in earnest in 2019 with the introduction of two new products to address electromagnetic field simulations and electrothermal co-simulations, though Cadence had been in the systems business for many years prior. The business line now represents around 13% of LTM revenue, up from 9% in 2019. 

Management claims that system software is a $50 billion market, with simulation being the relevant addressable market at about $8-$10 billion of the total. This market alone almost doubles Cadence’s EDA TAM. Furthermore, it is highly profitable, with margins above EDA.  Simulation is the main area of the market where Cadence’s core competency in computational software plays the biggest role (simulation is effectively applying computational software to a system), employing sophisticated algorithms. For instance, a “big system” to conduct thermal simulation of a phone for a traditional SD&A provider might include 40 million variables. For Cadence, with its capabilities to run over 50 billion variables for an advanced chip, this is child’s play.  

The bridge from chips to full systems has been Cadence’s early move into design and analysis for semiconductor packaging (3D-IC, chiplets). They now boast 80% share of a rapidly growing market. Hyperscalers like Amazon and Microsoft are investing hundreds of billions of dollars in AI and other modern data center applications. These bleeding edge products use a lot of advanced packaging, and all of them have a critical need to manage thermal issues like heat. 

With their enhanced capabilities, Cadence can get an order of magnitude improvement in simulation speeds versus traditional methods. Cadence’s almost unique ability to both simulate and optimize will open doors in many new markets like aerospace and defense, transportation, industrial, etc. Bringing to bear the advantages of AI and parallel processing through GPUs (for instance, to simulate the thermal impact of the shape of an airplane wing or the design of a data center) is opening the aperture even wider.

What’s more, Cadence’s move from chips to packages to systems is a one-way door. Legacy SD&A companies looking to punch back will find it hard to move into EDA because they would struggle to handle the exponential increase in variables that EDA entails.

Financial Results

Revenue growth has been strong and stable, producing an 11% CAGR since 2012. Breaking it down by business line since 2013 (when they first began to report under an approximation of the current structure):

They’ve seen the strongest growth in Functional Verification, at a 13% CAGR, just ahead of SD&A and IP, while Digital IC and Signoff grew 10% per year and custom IC Design and Simulation grew 8%. 

From a geographic perspective, revenues were as follows (note the reporting changed during the period, so we don’t have consistent data for all the regions throughout the timeframe): 

China posted the strongest growth at 22% per year, when they first split it out, followed by other Asian countries ex-Japan and China at 11%, the U.S. at 10%, other Americas at 10%, EMEA at 9%, and Japan, which has been flat (all since 2012, except China and Asia ex-Japan and China, which are both from 2017). It’s notable that the U.S. has inflected since 2019, growing at a 15% CAGR from that point forward.

Gross margin has shown to be highly stable on the back of solid revenue growth, with improvements in services margins driving some modest gains over time:

Management has effectively utilized the improved gross margin coupled with operating leverage over all the major operating expense buckets to drive higher operating margins:

Note that sales and marketing expenses, while significant, are quite a bit lower than R&D. This is mainly because Cadence is already well known in the industry and has almost nonexistent voluntary churn.

Returns on capital are excellent as capex is only around 3% of sales and working capital is highly negative mainly due to large deferred revenue balances. ROE is almost as impressive but dragged down by a conservatively financed capital structure (pristine, with net cash balances):

Management tends to use cash flow to buy back stock and complete some strategic M&A that enhances their core competency. Cadence has grown EPS at a 17% CAGR since 2012 on the backs of sales growth, margin expansion, and share buybacks, and despite a material increase in the tax rate beginning in 2022 due to regulatory changes.

Management’s longer-term goals are: 

• Double digit revenue growth.

• 50% incremental margin on new revenue. 

• Improving margins on top of revenue growth, leading to low- to mid-teens EBIT growth.

• 50% of free cash flow devoted to buybacks, with opportunistic purchases taking place when the share price is low enough.

• Shrinking share count coupled with EBIT growth producing high teens to low-20s EPS growth.

Cadence vs. Synopsys

As mentioned, Cadence’s biggest competitor is Synopsys (ticker: SNPS). While the two companies are quite similar, there are some differences, and they are becoming more pronounced: 

• Cadence has roots in analog semiconductors, whereas Synopsys came from a digital semiconductor foundation. Cadence believes these roots made it easier to shift to digital as the market developed. They liken it to an orchestra player moving into a rock band (easy to do), whereas a digital-first player is more like a rock and roller moving into an orchestra (hard to do).  

• Cadence has made an aggressive move over the last five years towards SD&A, a move that Synopsys has not copied. 

• Cadence claims to have 80% share in advanced packaging, mainly through its Allegro and Integrity tools, an area that is expected to grow for 10-20 years. This would imply a market size today for advanced packaging of around $500 million, based on Cadence’s $400 million in packaging related revenue. With this capability, Cadence is in great position to tackle the 3D-IC market, as they can offer package analysis and design as well as chip design and associated issues like thermal dissipation.

• Cadence does not emphasis its IP business nearly as much as Synopsys, and Synopsys has close to twice as many patents (Synopsys is well-known for its IP in interface technology, like PCI express, DDR, and USB, though they’ve also been investing in other areas like security and chiplets). This is purposeful on Cadence’s part, for several reasons:

  • IP is a lower margin business attributed to customers’ ability to choose between buying the IP from someone like Cadence or building it themselves. Unlike EDA, where customers really have no choice but to use Cadence or a competitor, this dynamic puts a natural ceiling on pricing for IP. 

  • Chip design (IP) is a core competency for customers, so it can produce channel conflict. 

  • IP requires significant resources to build and regularly update, with changing needs depending on the foundry partner and the process node. 

On the positive side, once a customer chooses to license an IP block, the revenue tends to be sticky, generally lasting for as long as the chip is produced. Cadence management therefore approaches IP from a niche perspective, choosing to play only in areas where they can create a truly differentiated product and extract decent economics. Their recent acquisition of IP from Rambus is a good example, as it provides Cadence with IP for high memory bandwidth that is well-suited to AI applications.

• Synopsys offers application security products in its software integrity business line, which are products that “enable security and development teams to build secure, high-quality software faster.” Cadence does not appear to have a similar offering.

• Cadence also claims to have the market leading emulation hardware (a rack that is used to emulate a chip).

The financial results also tell an interesting story. While Synopsys is the bigger company of the two ($6 billion in LTM sales vs. $4 billion for Cadence), its productivity is worse, as measured by revenue per employee:

Synopsys is also way behind on gross margin:

Some of this differential may owe to the revenue mix, as Synopsys has 26% of LTM revenue in the lower margin IP and System Integration category, plus another 9% in Software Integrity Products and Services (while we don’t know the margin positioning of this line of business, it is an area where Cadence does not compete and therefore introduces some mix effects). Synopsys also does not play in SD&A, which is one of Cadence’s highest margin business lines, and has a smaller footprint in the higher margin analog EDA business.

Dropping down to operating margin, we can see that Synopsys makes up some of the ground lost in gross margin, though it is still far behind Cadence: 

A closer look at the cost structures for the LTM period shows that Cadence reinvests a substantial amount of its nearly 1,000 bps gross margin advantage in R&D and sales and marketing, the two places we’re happy to see investment as it distances Cadence from the competition and expands their competitive moat, while picking up another 150 bps in lower non-value-added G&A relative to sales:

When we turn to our favorite metrics on business and management quality, ROIC and ROE, we see a similarly large advantage for Cadence, though both produce attractive returns in absolute terms (a positive sign for the health of the industry):

Cadence’s advantage on these metrics stems from its higher margins and a bit more financial leverage (that is, less net cash) offset in part by higher (that is, less negative) working capital. 

While Cadence appears to have a bit of an edge on the profitability front, the two are comparable when looking at revenue growth (both around 13.5% 5-year CAGRs). 

Valuation

Cadence is not a “cheap” stock in the traditional sense of having a low multiple on earnings. Here are the current and forward trading multiples: 

Investors have rerated Cadence’s multiple higher over the past decade. This is probably a function of several things: (1) the increasing financial strength of the business under Tan and now Devgan, (2) what is a now more apparent lack of cyclicality, and (3) higher growth prospects due to (a) increasing complexity, (b) a bigger customer base with systems customers like Amazon, Apple, and Tesla entering the chip design market, and (c) new technologies like AI.

The trading multiples for Synopsys are a bit lower at 67x trailing earnings and 50x expectations for fiscal 2025 (ending October). We’d argue that Synopsys deserves a bit of a discount due to its less attractive margin structure and returns on capital, as well as its lack of exposure to the higher growth and higher margin SD&A business.

We’d note that the current multiple could be construed as capitalizing “artificially depressed” earnings. This is because Cadence expenses its entire R&D costs upfront despite most of this spending representing an investment in the future growth of the business. If we were to assume that 60% of R&D spending was better considered as “capex,” in line with Wall’s comments that the R&D group spends more than half its time on new products, the accounting would more appropriately follow the “matching” concept of aligning expenses with revenues. In doing that, the LTM P/E would drop to a somewhat more palatable 43. We won’t take this line of thinking any further but do think it is a perspective worth considering.

Cadence seems to be a terrific business with an un-terrific price. The market appears to appreciate Cadence for its high-quality business and management, proven stability, and solid growth prospects. That is not a complete picture, however. Despite its heady headline multiples, we believe it’s “cheap” in relation to its prospects, both their absolute potential in terms of value creation and their likelihood of a favorable outcome. 

To help triangulate intrinsic value, we’ve constructed a simple cash flow model around the following assumptions:

• 5-year projections from the LTM. 

• Revenues grow at a CAGR of 10-20%. This compares to:

  • 19% growth in 2022.

  • 8% CAGR from 2013-2018, the weakest period in recent times, when management undertook its major turnaround efforts.

  • 13% CAGR since 2016.

  • 13-14% growth in 2023 YTD.

We argue growth is likely to inflect higher over the coming five years as the secular growth trends we’ve already discussed take hold.

• EBITDA margin (which includes stock compensation as an expense) expands to 37% in year five, or roughly 50 bps per year. This is a slower pace of improvement than management has accomplished over the past little while, as it grew EBITDA margins from 21% in 2013 to 24% by 2017, when Wall took over as CFO, and then to 27% by 2019, 33% by 2021, and over 34% in the LTM. That’s around 1,000 bps over 6 years, or over 165 bps per year. 

• Taxes at 25%.

• Capex at 3.1% of sales per year (the average since 2018).

• 50% of free cash flow to buy back shares, with the remainder going up as cash on the balance sheet and earning 4% interest.

• Exit P/E ranging from 25x-85x. This compares to the current trailing P/E of 82x and the average P/E since 2016 of 48x.

These assumptions produce the following range of outcomes:

In the unlikely scenarios where the multiple contracts materially, the outcomes generally range from manageable losses to single digit positive returns, not bad for a realistic downside. If an investor is reasonably optimistic about sales growth going forward and is comfortable that the market multiple will stay within historical ranges, the math is compelling.

Risks

Chinese competition. 

Upstart competition in China from the likes of Empyrean and Primarius have been around for a while with little impact. Cadence management calls these “some very small companies doing point tools.”  They do not have the capability to do full flow at advanced nodes with analog, digital, packaging, etc. Morgan Stanley estimates them at around 2.5% market share combined. 

The Chinese government could choose to finance a more significant competitor, and Chinese customers may prefer to do business with Chinese EDA and SD&A competitors, though we have not heard of anything real along either of these lines. 

China exposure.

Like almost every major tech company, Cadence has exposure to China (16% of revenues in the LTM). The tense relationship between the U.S. and China could lead to issues with Cadence providing its solutions there, though so far the restrictions on advanced AI chips and other technology has not had a major impact as it is focused on manufacturing, not design. It is not hard to imagine that changing, however, and we have seen some issues at the margin. For instance, Huawei was banned from using U.S.-based EDA tools in 2019 and has since created EDA tools internally for use at 14-nm nodes. It’s not inconceivable that others might be banned as well, especially if the 2024 U.S. Presidential election produces a new President. China has been a high growth market for Cadence (over 20% per year), so any meaningful restrictions would hurt.  

Chip alternatives.

Longer term, it is possible that silicon chips will be replaced by something better. Scientists have been trying to use other materials for a long time with limited success, but it’s not inconceivable that a replacement might come along. Efforts by companies like IBM to build quantum computers are showing some promise. It is hard to know what Cadence’s role might be in that world and whether management will be nimble enough to stay ahead of those changes.

Customer concentration.

Customer concentration is not a big issue, as no customer is more than 10% of revenues and the top 40 customers are roughly 55-60% of revenue. However, this does speak to some potential customer power, particularly if the tech industry continues to consolidate. There have been fears of consolidation before, and they’ve so far proven unfounded (or even positive). For instance, from 2014-2017, there was a lot of semiconductor M&A, and investors worried it would impact Cadence as the combined companies looked to eliminate duplicative costs. It turns out that no one fired their engineers, who are the lifeblood of the company, and in fact their improved financial strength led to a healthier industry with greater capabilities to invest in R&D for growth.

There is also a risk that some of the largest players might try to take EDA and SD&A in-house. While we don’t see that happening (in part because EDA is such a small expense overall and a great value in relative terms, and in part because EDA is so complex and built off decades of data and know-how), it remains a risk.

Open-source competition.

It’s possible that a company like Google, which is known to open source a lot of its internal technology, could invest in EDA and then open source its platform. This doesn’t seem to be a central risk, but it could impact Cadence at the margin.

Taxes.

Cadence has a somewhat unusual tax structure that has kept their tax rate low for a long time, but that seems to be changing for the worse. Rates in historically low tax regimes are going up due to a global agreement among 137 countries like Ireland and Hungary, where Cadence pushes a lot of earnings. Cadence has also begun amortizing R&D costs for tax purposes in the U.S. (rather than expensing them), which leads to higher taxes. They also moved their IP into Ireland in 2019 and have a $538 million deferred tax asset related to IP as of 12/31/22. There could be some risk around that move.

Appendix: Glossary

Here is a glossary of terms and acroynms we use throughout this document: 

• Advanced driver assistance system (ADAS): technologies that assist drivers with the safe operation of a vehicle. Through a human-machine interface, ADAS increases car and road safety. ADAS uses automated technology, such as sensors and cameras, to detect nearby obstacles or driver errors, and respond accordingly. ADAS can enable various levels of autonomous driving. Adaptive features may automate lighting, provide adaptive cruise control, assist in avoiding collisions, incorporate satellite navigation and traffic warnings, alert drivers to possible obstacles, assist in lane departure and lane centering, provide navigational assistance through smartphones, and provide other features.

• Advanced package: involves the collaboration of multiple chiplets within a single IC. These chiplets can be flexibly assembled in a mix-and-match manner, similar to "Lego building blocks", offering several advantages over conventional SoC designs. These benefits include the utilization of reusable IP, enabling the same chiplet to be employed in various devices. Additionally, the approach supports heterogeneous integration, allowing chiplets to be manufactured using different processes, materials, and nodes, each optimized for its specific function. Furthermore, the concept of KGD is implemented, whereby chiplets undergo testing before assembly, enhancing the yield of the final device.

• Artificial intelligence (AI)

• Augmented reality (AR)

• Basis points (bps): one hundredth of one percent.

• Bus: a communication system that transfers data between components inside a computer, or between computers. This expression covers all related hardware components (wire, optical fiber, etc.) and software, including communication protocols.

• Chiplet: a tiny IC that contains a well-defined subset of functionality. It is designed to be combined with other chiplets on an interposer in a single package. 

• Compounded annual growth rate (CAGR)

• Computational fluid dynamics (CFD): a branch of fluid mechanics that uses numerical analysis and data structures to analyze and solve problems that involve fluid flows. Computers are used to perform the calculations required to simulate the free-stream flow of the fluid, and the interaction of the fluid (liquids and gases) with surfaces defined by boundary conditions. CFD is important because it allows for the analysis of systems involving fluid dynamics without the need for expensive and timely physical experiments.

• Conjugate gradient method: an algorithm for the numerical solution of particular systems of linear equations, namely those whose matrix is positive-definite. The conjugate gradient method is often implemented as an iterative algorithm, applicable to sparse systems that are too large to be handled by a direct implementation or other direct methods such as the Cholesky decomposition. Large sparse systems often arise when numerically solving partial differential equations or optimization problems.

• Digital signal processors (DSPs): a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. The goal of a DSP is usually to measure, filter or compress continuous real-world analog signals. Dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as mobile phones because of power consumption constraints.

• Double data rate (DDR): a computer bus that transfers data on both the rising and falling edges of the clock signal.

• Electronic design automation (EDA): as defined in the main body.

• Fin field-effect transistor (FinFET): a multigate device, a MOSFET built on a substrate where the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a double or even multi gate structure. FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal oxide semiconductor) technology. FinFET is a type of non-planar transistor, or "3D" transistor. They are the dominant gate design at 14-nm, 10-nm, and 7-nm process nodes.

• Gate all around (GAA) or surrounding-gate transistor: the successor to FinFETs, as they can work at sizes below 7-nm. They are similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, GAA FETs can have two or four effective gates.

• General and administrative costs (G&A)

• Hyperscaler: hyperscale in computing is the ability of an architecture to scale appropriately as increased demand is added to the system. This typically involves the ability to seamlessly provide and add compute, memory, networking, and storage resources to a given node or set of nodes that make up a larger computing, distributed computing, or grid computing environment. Hyperscale computing is necessary in order to build a robust and scalable cloud, big data, map reduce (a programming model and an associated implementation for processing and generating big data sets with a parallel, distributed algorithm on a cluster), or distributed storage system and is often associated with the infrastructure required to run large distributed sites such as Google, Facebook, Twitter, Amazon, Microsoft, IBM Cloud or Oracle.

• Integrated circuit (IC), chip, or microchip: a set of electronic circuits on one small flat piece of semiconductor material, usually silicon. Large numbers of miniaturized transistors and other electronic components are integrated together on the chip. This results in circuits that are orders of magnitude smaller, faster, and less expensive than those constructed of discrete components, allowing a large transistor count.

• Intellectual property (IP) 

• Internet of things (IoT): devices with sensors, processing ability, software and other technologies that connect and exchange data with other devices and systems over the Internet or other communications networks.

• Known good die (KGD): refers to an IC or semiconductor die that has been thoroughly tested and verified to meet the required specifications and quality standards before it is integrated into a larger package or assembly. The term emphasizes the certainty that the individual die is functional and meets its intended performance criteria. The use of KGD is particularly important in advanced packaging technologies, where multiple chiplets or dies may be integrated into a single package. Ensuring that each individual die is known to be functional before assembly helps prevent the integration of defective components, reducing the likelihood of manufacturing defects in the final product. 

• Last twelve months (LTM) 

• Machine learning (ML): a field of study in artificial intelligence concerned with the development and study of statistical algorithms that can effectively generalize and thus perform tasks without explicit instructions. ML approaches have been applied to large language models, computer vision, speech recognition, email filtering, agriculture, and medicine, where it is too costly to develop algorithms to perform the needed tasks. The mathematical foundations of ML are provided by mathematical optimization (mathematical programming) methods.

• Matrix multiplication: a binary operation in mathematics (particularly linear algebra) that produces a matrix from two matrices. For matrix multiplication, the number of columns in the first matrix must be equal to the number of rows in the second matrix. The resulting matrix, known as the matrix product, has the number of rows of the first and the number of columns of the second matrix.

• Mergers and acquisitions (M&A)

• Metal-oxide-semiconductor field -effect transistor (MOSFET): a type of field-effect transistor, most commonly fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. The main advantage of a MOSFET is that it requires almost no input current to control the load current, when compared with bipolar transistors. The MOSFET is by far the most common transistor in digital circuits, as billions may be included in a memory chip or microprocessor.

• Multigate device: a 3D transistor structure used in the design and manufacturing of ICs. It is the evolution of the traditional planar MOSFET.

• Node: As technology progressed and chip foundries improved their capabilities, they produced chips that incorporate smaller and smaller features on each layer of the chip, with tighter spaces. As they decreased minimum sizes and tightened the spacing, foundries could either reduce the size of the chip while maintaining the same performance or keep the chip the same size and increase the performance. Each new generation process is called a node, designated by the process’s minimum feature size (currently measured in nm) of the process’s transistor gate length. Since 1994, however, the designations have become less homogeneous across foundries as the technology became more complex. Even so, they still give a good indication of the size of the gate length. 

• Peripheral component interconnect (PCI): a local computer bus for attaching hardware devices in a computer. Attached devices can take either the form of an IC fitted onto the motherboard (called a planar device in the PCI specification) or an expansion card that fits into a slot.  

• Personal computer (PC)

• Power, performance, and area (PPA)

• Printed circuit boards (PCBs): a medium used to connect or "wire" components to one another in a circuit. It takes the form of a laminated sandwich structure of conductive and insulating layers. PCBs are used in nearly all electronic products.

• Nanometers (nm): a unit of length equal to one-billionth of a meter. The diameter of a typical human hair is about 50,000 to 100,000 nanometers.

• Radio frequency (RF): the oscillation rate of an alternating electric current or voltage or of a magnetic, electric or electromagnetic field or mechanical system in the frequency range from around 20 kHz to around 300 GHz. This is roughly between the upper limit of audio frequencies and the lower limit of infrared frequencies. These are the frequencies at which energy from an oscillating current can radiate off a conductor into space as radio waves, so they are used in radio technology, among other uses. 

• Research and development (R&D)

• Return on equity (ROE): a measure of levered profitability and capital efficiency calculated by dividing net income into average shareholders’ equity.

• Return on invested capital (ROIC): a measure of unlevered profitability and capital efficiency calculated by dividing EBITA into average invested capital (calculated as the sum of net debt, preferred equity, non-controlling interests, and shareholders’ equity).

• Semiconductor: an electronic component that relies on the electronic properties of a semiconductor material (primarily silicon, germanium, and gallium arsenide, as well as organic semiconductors) for its function. Its conductivity lies between conductors and insulators. Semiconductor devices are typically ICs like computer processors, microcontrollers, and memory chips, though they can also be single discrete components.

• Serializer/Deserializer (SerDes): a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction.

• System design and analysis (SD&A): as defined in the main body. 

• Systems-on-chip (SoCs): an IC that integrates most or all components of a computer or other electronic system. These components almost always include on-chip central processing unit (CPU), memory interfaces, input/output devices and interfaces, and secondary storage interfaces, often alongside other components such as radio modems and a graphics processing unit (GPU) – all on a single substrate or microchip. SoCs may contain digital, analog, mixed-signal, and often radio frequency signal processing functions (otherwise it may be considered on a discrete application processor).

• TAM: total addressable market.

• Transistor: a semiconductor device used to amplify or switch electrical signals and power. It is one of the basic building blocks of modern electronics. It is composed of semiconductor material, usually with at least three terminals for connection to an electronic circuit. A voltage or current applied to one pair of the transistor's terminals controls the current through another pair of terminals. Because the controlled (output) power can be higher than the controlling (input) power, a transistor can amplify a signal. Some transistors are packaged individually, but many more in miniature form are found embedded in ICs.

• Universal serial bus (USB): an industry standard that allows data exchange and delivery of power between many various types of electronics. It specifies its architecture, in particular its physical interface, and communication protocols for data transfer and power delivery to and from hosts, such as PCs, to and from peripheral devices, e.g. displays, keyboards, and mass storage devices, and to and from intermediate hubs, which multiply the number of a host's ports.

• Virtual reality (VR)

• Year-to-date (YTD)

Appendix: Cadence Segment Descriptions

Custom IC Design and Simulation 

Our custom IC design and simulation offerings are used by our customers to create schematic and physical representations of circuits down to the transistor level for analog, mixed-signal, custom digital, memory and RF designs. These representations are verified using simulation tools optimized for each type of design, including the design capture environment, simulation and IC layout within the Virtuoso custom IC design platform. Other tools in the custom IC portfolio are used to prepare the designs for manufacturing.

The Virtuoso Advanced-Node Platform adds functionality to the base Virtuoso package to enable the use of three-dimensional transistors (“FinFETs”), multi-patterning and other technologies required for advanced designs. The Virtuoso RF Solution addresses the challenges of RF design across chip, package and board. The Spectre Simulation Platform provides large-scale verification simulation. The Virtuoso System Design Platform enables engineers to design and verify concurrently across the chip, package and board.

Digital IC Design and Signoff

Our digital IC design and signoff solutions are used to create logical representations of a digital circuit or an IC that can be verified for correctness prior to implementation (please refer to the discussion under “Functional Verification” below). Once the logic is verified, the design representation is implemented, or converted to a format ready for silicon manufacturing, using additional software tools within this category. The manufacturing representation is also analyzed and verified. Our digital IC design and signoff technology suite provides a full flow to achieve power, performance and area (“PPA”) design targets, and includes three major categories: logic design, physical implementation and signoff. Our logic design offering is comprised of logic synthesis, test and equivalence checking capabilities and is typically used by customers to create and verify designs in conjunction with our functional verification capabilities. The offering includes the Genus Synthesis Solution, a logic synthesis offering that provides fast throughput while also offering high quality results, and the Joules RTL Power Solution, which delivers fast power analysis while preserving near-signoff accuracy. We also offer the Modus software solution, which reduces SoC design-for-test time. Our physical implementation offering comprises tools used near the end of the design process, including place and route, optimization and multi-patterning preparation. The Innovus Implementation System is a physical implementation offering that delivers fast design turnaround time while also delivering improved PPA characteristics. This offering enables customers to address the technology challenges of the latest semiconductor advanced-process nodes, create a physical representation of logic models and prepare a design for signoff.

Our signoff offering is comprised of tools used to sign off the design as ready for manufacture by a semiconductor foundry, which provides certification for this step. This offering includes the Tempus Timing Signoff Solution, Voltus Power Integrity Solution, Quantus Extraction Solution and Pegasus Physical Verification System. Our design-for-manufacturing products are also included in our signoff offering and are used by customers to address manufacturing and yield issues as early in the product development process as possible.

Functional Verification

Functional verification products are used by our customers to effectively and efficiently verify that the circuitry or the software they have designed is consistent with the functional specification. Verification is largely done throughout the design process, with the objective of identifying as many potential functional problems as possible before manufacturing the circuitry, thereby significantly reducing the risk of discovering a costly error in the completed product. Our Verification Suite includes four primary verification engines, starting with the JasperGold Formal Verification Platform and Xcelium Parallel Logic Simulation Platform, which are used in the early stages of design verification, often at the IP and subsystem level. Once the design is more mature, with early formal and simulation verification tasks performed, verification engineers deploy our Palladium Enterprise Emulation Platform and Protium FPGA-Based Prototyping Platforms for more comprehensive chip verification, often running low-level embedded software on top of a model of the chip, to provide for proper functionality before silicon manufacturing. These engines are used for early bug detection, verification of block-level functionality, verification acceleration and emulation of system-level functionality, system-level power exploration, analysis and optimization, and system-level prototyping for hardware/software co-verification. Our Palladium platform provides high throughput, capacity, data center reliability and workgroup productivity to enable global design teams to develop advanced hardware-software systems. The Protium platform leverages a common front end with the Palladium environment to move designs rapidly from emulation to the prototyping stage, allowing for software development to start weeks to months earlier than otherwise possible. These engines are also supported by other verification tools that provide an environment that allows for effective verification throughput and management, including verification planning and metric tracking, testbench automation, debugging and software-driven tests, enabling our customers to coordinate verification activities across multiple verification engines, teams and locations for effective verification closure.

IP

Our IP offerings consist of pre-verified, customizable functional blocks, which customers integrate into their ICs to accelerate the development process and to reduce the risk of errors in the design process. We offer many types of IP, including Tensilica configurable digital signal processors (“DSPs”), vertically targeted subsystems for AI, audio/voice, baseband and vision/imaging applications, controllers and physical interfaces for standard protocols and analog IP. Our design IP portfolio also includes solutions for high speed SerDes, PCI, USB and many other standards. We also offer a broad range of Verification IP (“VIP”) with memory models, which model the expected behavior of many industry standard protocols when used with verification solutions and are complementary to our design IP offerings. Our VIP and accelerated VIP are used with our full suite of functional verification engines to emulate and model the expected behavior and interaction of standard industry system interface protocols including DDR, USB, and PCI Express in silicon. Our customers also use our System VIP offerings to perform full system-level chip verification.

System Design and Analysis 

Our system design and analysis offerings are used by our customers to develop PCBs and advanced IC packages and to analyze electromagnetic, electro-thermal and other multiphysics effects.

The capabilities in the Allegro System Design Platform include PCB authoring and implementation, IC package and system-in-package design, signal and power integrity analysis, and PCB library design management and collaboration. The need for compact, high-performance mobile, consumer and automotive design with advanced serial interconnect is driving the technology evolution for our PCB offerings. For mainstream PCB customers, where individual or small team productivity is a focus, we provide the OrCAD family of offerings that is primarily marketed worldwide through a network of resellers. The speed and close proximity of signals on silicon, through packages to boards, and through connectors and cables, exposes these communications to various kinds of interference, generates heat and emits electromagnetic radiation. Careful analysis is required for these systems to work as designed under a wide range of operating conditions and within compliance of standards and laws. The complexity of these devices and signal transmissions requires analysis and simulation throughout the product lifecycle to meet these objectives. Our Clarity 3D Solver for electromagnetic and power electronics analysis and simulation, as well as our Celsius Thermal Solver, provide the foundation for multiphysics analysis technology, with complete electrical-thermal co-simulation for electronic systems from ICs to physical enclosures. Our Fidelity CFD Software solution expands our ability to meet the growing design challenges of electronic and systems companies. Our comprehensive suite of CFD solutions enable our customers to extend their multiphysics analysis workflows to address simulation and analysis challenges for applications such as aerodynamics, hydrodynamics, propulsion, turbomachinery, heat transfer, and combustion.

The addition of our computational molecular modeling and simulation solution with our acquisition of OpenEye leverages our computational software expertise and expands our ability to address various challenges of drug discovery faced by pharmaceutical and biotechnology companies.

Disclosures 

The information contained herein has been derived from public information believed to be reliable but the information is not guaranteed as to accuracy and does not purport to be a complete analysis of any security, company or industry involved. All data and analysis are unaudited and should not be used as the basis for any investment decisions. Neither the advisor, nor any of its officers, directors, partners, contributors, employees or consultants, accept any liability whatsoever for any direct or consequential loss arising from any use of information in this analysis. The user of the information assumes the entire risk of any use it may make or permit to be made of the information. 

Neither the advisor nor any of its employees holds a position with the issuer such as employment, directorship, or consultancy.

The adviser, through accounts that it advises, may hold an investment in the issuer's securities.

Catalyst

Continued strong earnings and higher revenue growth