|Shares Out. (in M):||714||P/E||N/M||N/M|
|Market Cap (in $M):||920||P/FCF||12.95||7.66|
|Net Debt (in $M):||-240||EBIT||66||115|
|TEV (in $M):||679||TEV/EBIT||10.23||5.93|
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Niche Semiconductor IP Firm Leveraging Leadership to Create Scaled Marvell-Like Business
1) Thesis Description
Alphawave IP (AWE) is a semiconductor firm focused on developing high-speed wired connectivity IP for data infrastructure end markets. The complexity at the leading edge of semiconductor design is necessitating a new tool kit for wired connections inside and between chips as traditional methods of scaling down wiring no longer yield competitive results. The company’s founders have extensive knowledge of this niche domain (SerDes) and have quickly developed a unique connectivity IP portfolio, already a year or so ahead of competitors, which has allowed them to rapidly gain share in a short period of time. While the company IPO’d in May of ’21 and have incurred erroneous accusations of illegitimacy/self-dealing in the press, the adoption of their solutions is expected to truly materialize in ’23 as design wins from ’19-’21 scale up into full production. With their lead in connectivity IP accelerating, Alphawave is now undergoing a transformation to provide entire connectivity chiplet design solutions in addition to licensing following the acquisition of OpenFive, a SoC design firm. This transaction should create a scaled firm in the style of Marvell as the adoption of chiplets massively increase the number of connection points within data centers/networks and therefore AWE’s market.
The thesis is as follows:
1) At the current price of ~£116p/share, the market assumes no revenue growth beyond their ’23 guidance of $325M-$360M and 40%-45% margin outlook on a ~4.5x EV/EBITDA valuation multiple. Valuation ranges from £175p/share to £2,300p/share over five years, with scenarios ranging from no growth/no Chinese revenue to ~$3.5B in revenue (half of MRVL) at a FCF valuation on par with Marvell (~25x).
2) An opportunity is available due to several reasons:
a. Alphawave’s ’17 founding, Chinese exposure and overall success coupled with a mid-’21 IPO, still draws significant investor skepticism as to the validity of the enterprise. Alphawave was founded in ’17 by three engineers with decades of experience starting up and monetizing semiconductor IP companies, selling their last SerDes (serial-deserialization) IP firm, V Semi, to Intel in ’12. Deep experience in a niche, and growing segment of the IP market coupled with clever strategies to onboard two large Chinese customers (more on that below) has resulted in revenue over $100M from ~28 customers in just a few years. This pace of growth and market presence is almost unheard of in the semi IP market and with its IPO conducted so early in the life of the company, the event was generally perceived as an exit for the founders before their technology phased out. However, since then, Alphawave now boasts Microchip, Broadcom, Google, Microsoft, and Intel as customers. Further, foundries TSMC, Samsung and Intel have approved AWE as a top-tier vendor. Given the recency of these new wins and the roughly two-year design cycle for new Application-Specific Integrated Circuits (ASICs), customer volumes/royalty revenue have yet to show up to Alphawave in scale as most of the revenue base currently consists of license sales and non-recurring engineering fees. Material growth in royalty revenue is expected from almost all AWE’s customers as their solutions are well ahead of competitors and customer physical chip production/delivery is highly probable. Further, discussions with industry participants indicate that leadership at AWE is legitimate, highly thought of and their unique technical/business strategies put them in a league of the largest IP players in the industry (SNPS, CDNS, ARM). Given the market’s appetite for recent IPO’s, significant (current) Chinese exposure and the lack of operating history, AWE trades at a ~4.5x EV/EBITDA (~4.75x EV/FCF), while top tier firms are typically valued at 10x-20x (ex. covid timeframe).
b. Late September ’21 ‘hit piece’ exaggerated the materiality of founder-related transactions and implied nefarious intent, when in actuality everything was above-board and fully disclosed. At the time of the IPO, Alphawave’s two big subscription license sales were to Chinese firms, VeriSilicon and WiseWave. Disclosed in the prospectus was WiseWave’s ~7% ownership of AWE and their joint venture in China. While not directly related to the founders, the VeriSilicon CEO is the brother-in-law of Dr. Sehat Sutardja, the co-founder of Marvell who is also a ~13% owner of AWE. From discussions with industry participants, this was an above-board transaction as the commercial relationship with VeriSilicon preceded any investment from Dr. Sutardja and while not disclosed in the prospectus since the relationship was one degree removed, management nonetheless discussed it with investors. Further, Alphawave’s Chairman John Holt, was a co-founder and director of Achronix, an AWE customer amounting to ~$6M in ’19 and only ~$1.8M in ’20 on a ~$30M revenue base. Achronix should amount to only ~$1M of revenue in ’22. Importantly, Mr. Holt resigned from Achronix in July of ’21. Despite these nuances, an article written in late September ’21 highlighted these points as if they were obscured from the public, all the while failing to note the appropriate disclosures in the prospectus and the fact that management communicated to investors about these relationships with total transparency at the time of the IPO. Following publication of the article, AWE dropped ~50% and has yet to recover despite management clearly discussing the nuances for the last year. Subsequently, a material subset of financial participants continue to believe this company is illegitimate or has less than reputable management. From their filings, related party transactions outside the WiseWave JV (more on that below), now amount to ~2% of revenue versus the ~20% at the time of IPO. This legacy concern is likely one of the top two biggest reasons for a mispricing of AWE, despite the robust growth in blue-chip semi customers utilizing the company’s technology and management’s forthrightness.
c. Fears of Chinese customer and investor overexposure should diminish rapidly given WiseWave’s exit and strong growth outside of the region. Entering the Chinese market aided AWE in scaling up quickly, given the appetite of the country’s semiconductor industry for access to leading edge technology. VeriSilicon and WiseWave subscription deals amounted to a potential ~$255M in revenue over several years (including a possible ~$105M extension from WiseWave) and yet trailing 12-month AWE revenue ex-China equated at the time of IPO to ~$35M. WiseWave’s subscription deal was structured as a JV, with the PE Firm (Wise Road Capital) taking ~7% ownership in AWE (along with dual capital commitments). Chinese-derived revenue equated to ~60% of total at YE’21 and has since declined to 35%-40% in 1H/22. However, with the acquisition of OpenFive (US company with majority of sales in NAM), post-CFIUS approval resulted in both Alphawave and WiseWave agreeing to reduce its ownership and keep its commercial relationship steady. As such, the company no longer expects WiseWave to exercise its license extension in ’23 (already embedded in guidance) and cease its JV capital commitments. The PE firm has already exited 1/3 of its position in AWE with ownership now at ~4%. We anticipate WiseWave exits entirely by the end of next year, representing a possible re-rating as the stigma of their ownership goes away. Additionally, given the slower pace of revenue growth in China (possibly flattish) and over ~55% annual growth for AWE ex-China and OpenFive’s ~80% NAM exposure, we expect NAM revenue to increase to 60%-70% of revenue and Chinese related revenue to decline to 20%-25% in ’23 and 10%-15% in ’24. Far below their previous expectation of ~30% long term. The current regional overexposure and escalating tensions between the West are likely the biggest reason for Alphawave’s mispricing and the trajectory of the business suggests this operational risk should be substantially lower in the future more quickly than most anticipate. Importantly, any effective restrictions on leading edge semis going into or being made in China by the US/West would simply accelerate the reduction in materiality of Chinese revenue on AWE as opposed to creating a going concern risk that many believe would occur.
d. Acquisition of OpenFive underestimated by investors as it allows Alphawave to move up into the larger chip design market by providing complete chiplet designs as opposed to just IP products. In AWE’s prospectus, the stated reason for the IPO was to have access to capital to accelerate their market ambitions providing higher-value connectivity solutions predominantly at the chiplet level. OpenFive was the ’20 creation of Open Silicon and SiFive (a RISC-V fabless semi firm), a scaled firm of ~300 engineers providing domain-specific chip designs for RISC-V and ARM architectures. Alphawave worked with SiFive to carve out the design business as it became a stranded asset within SiFive as they focus solely on RISC-V CPUs, purchasing it for ~$210M (10x-12x EV/EBITDA) in early ’22. With greater chip complexity, a wider variety of architecture libraries and a more diverse customer base focused more on technical differentiation rather than technical development, outsourced custom design solutions are expanding rapidly in the marketplace. The transaction almost triples AWE’s customer base to ~80 representing a large cross-sell opportunity, doubles IP products to ~155 encompassing a wider range of connectivity products and expands the company’s competitive advantage as they can solidify their first-to-market IP position into fully designed chips. More importantly, the combination massively expands the company’s revenue opportunity set as IP products typically garner $2M-$5M per license plus royalties, while designed chiplet solutions generate $30M-$50M per design (plus royalties and larger support fees) with easier sales cycles given that customers can simply approve a complete chip component based on their specs versus integrate an AWE IP product into their or another third-parties design. Further, design work is closely tied to a customer’s less cyclical R&D spending, which affords Alphawave greater visibility, more durable earnings, and in turn, less terminal value risk at maturity. With the data infrastructure end markets having more complex requirements and massive customers, a custom silicon design division was critical for Alphawave scaling up the business to grow beyond its IP and more effectively compete with Marvell and Broadcom.
e. Skepticism towards rapid growth over the next 3-5 years fails to account for the accelerating adoption in the data center of 112G SerDes and chiplets, several single technology/function chips connected together versus System on a Chip (SoC). Alphawave’s technology is predominantly focused on the leading-edge nodes for high-speed data transfer across wires in and between chips for use in data centers (transfer and storage), 5G telecom infrastructure and AI. The company’s latest technology is at the 112G node, at least a year ahead of competitors, which is now at the base of the s-curve of adoption in the data center, an industry with a market of hundreds of millions of connection points necessitating high-speed transfer. However, an underestimated growth vector, and just as impactful is the industry transition to chiplet designs. Manufacturing yield/complexity issues with SoCs at the leading edge have driven semi fabs/designers to split the functions of a system on a chip into smaller parts allowing them to have various technology nodes connected into a single equally capable product with less cost. Translating this to Alphawave, instead of one SoC with one connection point and therefore one license/royalty unit, a chiplet doing the same job combining 5-10 different components increases the amount of connection IP licenses required. In essence, transition to chiplets has the potential to expand the connection points within several data infrastructure verticals, and AWE license/royalty revenue, by 5x over time (even more if chiplet components are interconnected). While early in this transition, adoption of chiplet designs is expected to grow exponentially over the next few years now that industry participants have agreed on a standard for chiplet connections, Universal Chiplet Interconnect Express (UCIe), derisking both the market for chiplets and Alphawave’s technology solutions utilizing said standard.
f. UK listing allows for flexibility but obscures the company’s North American roots/operating style, and limits interest from US technology investors/Sell-side firms. Alphawave IPO’d on the London exchange for several reasons. The UK domicile allows greater flexibility to sell into the US and Asia with lower risk of restrictions. Second, the greatest supply of SerDes specific engineers is in London and the company’s headquarters in Ontario, Canada. Third, was to entice local investors by drawing analogies to ARM. An analogy which has since changed as AWE acquired OpenFive, but necessary given the differing market focus (data infrastructure vs. ARM’s mobile markets) and evidence of ARMs struggles to gain profitable share in data centers as just an IP firm (a SoftBank induced initiative). However, the largest pool of technology capital is in the US, where knowledge of AWE is limited. A secondary effect of this UK domicile is minimal Sell-side coverage, currently at three analysts. Additionally, its UK domicile may be a source of mispricing given the volatility in the country recently and a cursory belief Alphawave is European run, a generally unappealing proposition to US investors. At its core, AWE is a Canadian company with financials in US dollars and soon, most of its revenue from US customers, that happens to be listed in the UK. As the company grows in size and mind share, particularly as they win more NAM customers, we would anticipate a possible NASDAQ listing in the coming years and at the very least greater investor outreach in the US.
g. Significant founder and board ownership limit share liquidity and near-term investor interest. The three founding engineers own ~40%, followed by Dr. Sehat Sutardja with ~13% and John Holt/WiseWave at 2%/4% each, totaling 55%-60% of shares outstanding. Adding to ownership concentration, despite the IPO lock up ending late ’21, insiders only sold down their position minimally and Dr. Sutardja actually increased his position with shares in the £120p-£140p range. Interestingly, AWE comprises ~10% of the Sutardja family’s net worth. While share liquidity for investors is somewhat limited (250K-500K shares daily), greater interest in the semiconductor sector or the company, an exit by WiseWave, and/or modest secondary sales by insiders, or a listing on the NASDAQ would increase the amount of shares available and actively traded.
3) The largest micro risks in the name are customer concentration, execution issues with the OpenFive acquisition, technology development issues and loss of design wins, and overall technological obsolescence. The largest macro risks are the levels of data center/hyperscaler spending, 5G infrastructure buildout, chiplet adoption, and China/West tensions/restrictions.
2) Business Analysis
A Brief History – Founded by Successful SerDes Engineer-Entrepreneurs, Targeting the Paradigm Shift in Chip Connectivity Development/Design
Alphawave was founded in ’17 by Tony Pialis, (CEO), Raj Mahadevan (COO) and Jonathan Rogers (SVP Engineering). All three were previously at Intel from ’12-’17 after their company V Semi was acquired. V Semi was a multi-standard SerDes IP development firm. Prior to V Semi in the early ‘00s, the team met at Snowbush Microelectronics, an analog IP licensing and design firm for high-speed connectivity.
All of these companies utilized analog-based analysis/methods for scaling down wiring to and from a chip utilizing SerDes (serial/deserialization). While not a comprehensive description, SerDes is a method of high-speed data transfer that is channeled through specially engineered transceivers at each chip connection point and is a necessity for any semiconductor.
Essentially, communication between two chips with multiple I/O connections can be done in parallel, sending data through ports at the same time to the receiving chip/chips. However, if one has 5 I/O ports on a chip, sending data out simultaneously consumes a lot of power, can have electromagnetic interference, and reduces functionality if limited on the number of ports in a chip, all resulting in a bigger/more complex chip.
SerDes takes all the data on the chip that is to be transferred, packages it up (serializes) in the transceiver, sends the data through one I/O port, which is then broken back down (deserialized) in the receiving chip. This results in lower power consumption and EM interference, fewer I/O ports required to send an equivalent amount of data and ultimately a smaller, less complex chip. Using parallel transmission would also relegate other chip components to be clocked at the same frequency, a design constraint that severely limits a chip's performance/flexibility.
SerDes was created in ‘90s and since then data rate throughput has increased exponentially. But as chips scaled down from 28nm transistors to 7nm, traditional methods of essentially just shrinking the wiring started to show issues generating sufficient data transfer levels with acceptable EM interference and wire resistance/capacitance. In chip design, the physical wires between them became the bottleneck to faster speeds and lower power consumption.
This is forcing an analog engineering domain (PHY, the Physical Layer) into a mixed-signal world as digital solutions are required to meet the analog challenges at the leading edge. As such, SerDes designers utilizing digital signal processing (DSP) to manage these problems is a niche within a niche. In fact, below 7nm analog SerDes methods break down substantially. Notably, Alphawave was the first IP vendor to demonstrate functional silicon SerDes solutions at 7nm in ’18. Leading edge designs are now at 3nm.
During their time at Intel, the founders would have had visibility into this scaling problem as the company was the leader in high performance server applications in the early ‘10s. However, digital processing technology for a niche like SerDes was likely too nascent for a company like Intel to dedicate resources toward.
This is where Alphawave has developed unique IP by building their products off a DSP ‘chassis’. Said another way, the company designed a single, configurable digital signal processor joined to an analog SerDes wiring solution. This results in a single product that can be configured for many customers’ requirements on speed (up to 112Gbps), network protocol, number of pins, power consumption, reach size and API libraries.
Alphawave has DSP IPs, Integrated Product IPs, Chiplet IPs, and OpenFive services/IP in total 155 IP products and comprehensive chip design solutions with over 80 customers (~28 from Alphawave as of 1H/22). Approximately 70% of revenue is derived from product IPs.
DSP Connectivity IP Cores
The DSP IPs in AWE’s portfolio cover speeds between 1Gbps up to 112 Gbps across multiple reaches, and network protocols. The next node under development is 224G, which would likely contain wired as well as silicon photonic solutions. Products are the ZeusCORE, AlphaCORE, ApolloCORE DieCORE100 and AthenaCORE.
Integrated Product IP Cores
Integrated IPs are semi-customizable full product solutions for repeaters in the connectivity channel (electrical and optical). Examples include the OctalCORE800 and HexaCORE1600 ethernet products. These ethernet (wired and optical) IP products acquired from AWE’s purchase of Precise ITC in late ’21.
Chiplet IP Cores
Chiplet IPs build off the DSP IPs with a combination of designs utilizing die-to-die interfaces and varying DSP SerDes Cores. Names for these products are the ZeusCHIP, AlphaCHIP and ApolloCHIP. AWE sold its first chiplet IP in late ’21.
Open Silicon (founded almost 20 years ago) was purchased by SiFive, a RISC-V CPU design/IP firm in ’20 and turned into OpenFive. SiFive is venture backed by Intel, AMD, Samsung, Coatue Partners and others, recently raising $175M at a $2.5B valuation. In a lead up to a potential IPO, SiFive realized that a design house was detracting from full-on development of RISC-V CPU IP and unlikely to help in accelerating the RISC-V ecosystem. As such, SiFive adopted a pure IP model since they directly compete with ARM and sold OpenFive to Alphawave for ~$210M (10x-12x EV/EBITDA) in early ’22. Top line growth of OpenFive over the last few years is unknown, however, two years ago the company had ~250 employees increasing to ~300 in ’22, equating to ~10% per annum while likely being under-resourced.
OpenFive develops domain-specific custom System-on-a-Chip (SoCs) and chiplets across every stage of design, architecture, logic, physical, system, software, and IP. The company partners with fabs (TSMC Design Center Alliance member) to deliver fully tested chips. Both OpenFive and AWE joined Intel’s Accelerator program in ’22. Customer base is more than 50 entities and to date has completed over 350 tapeouts in addition to over 150 million chips delivered.
Going forward, Alphawave plans to redirect their SoC design expertise and develop chiplet designs/IP. OpenFive’s portfolio is highly complementary to AWE, with memory and chiplet interface IP and a license agreement with SiFive for RISC-V IP.
Alphawave’s revenue is based on a technology licensing model of licensing fees, non-recurring engineering fees (NRE), support and maintenance, and royalties.
Pro forma OpenFive, over 55% of revenue is from NAM, 20%-25% from China, 15%-20% APAC and ~10% from EMEA. Pro forma, AWE licensing should comprise ~55% of revenue, OpenFive ~40% and support ~5%.
Management History – Significant Co-Founder Ownership (~40%), Impressive Management and Shareholders
Tony Pialis, (CEO), Raj Mahadevan (COO) and Jonathan Rogers (SVP Engineering) are the founders of Alphawave. All three were previously at Intel from ’12-’17 after their company V Semi was acquired. Prior to V Semi in the early ‘00s, the team met at Snowbush Microelectronics, an analog IP licensing and design firm for high-speed connectivity. At Intel, the team recognized the potential for digital signal processing for SerDes and once their pay packages vested, promptly left the company to start AWE. Tony and his team are widely regarded as great engineers in the industry for SerDes/high-speed signaling.
Dr. Sehat Sutardja joined the Board of AWE in ’19 and at the time of the IPO had ~12% ownership in the business. In mid-’22, he increased his position with shares in the £120p-£140p range. Interestingly, Alphawave comprises ~10% of the Sutardja family’s net worth. The Sutardja family has several investments across the semiconductor industry, but their ownership of AWE appears to be an outsized bet. The VeriSilicon relationship was already established before the Sutardja’s were involved but in either case the company now should only generate ~$3M to AWE this year.
John Holt, the Board Chairman, owned ~4% of AWE at the time of the IPO and has since lowered his position to ~2%. Mr. Holt is the founder and former director of Achronix Semiconductor (stepped down in July ’21). Achronix was an early user of Alphawave IP, but since ’19 revenue generated by this counterparty has dropped to ~$1M per annum.
WiseWave at the time of IPO owned ~7% of AWE with a JV known as the CPP (Chinese Product Partnership). With the acquisition of OpenFive, both AWE and WiseWave agreed to limit new business and WiseWave has already started rationalizing their position in the company now at ~4%.
Directors and key personnel are expected to be compensated $3M-$4M this year with no incremental equity shares.
The executive team and insiders own 55%-60% of AWE.
Customer Dynamics – High-Speed Demands, Chip Complexity and Speed to Market Driving Customers to In-House Design for Custom Solutions, While Outsourcing Specialized and ‘Difficult’ IP/Design such as SerDes
Alphawave’s customers end markets are predominantly data centers and networks (75%-80%), 5G infrastructure (~10%), solid-stage storage (~5%), and AI (~5%). The company in total has ~80 customers, including most of the top semiconductor firms and hyperscalers. Approximately 50% of revenue is derived from the top 3 customers for AWE, which is expected to decline with the integration of OpenFive, which has a much wider customer base. With only a few hundred potential customers, a large sales force is not required.
AWE’s solutions are at the high-end of the market, targeting the most demanding compute/data transfer use cases, whose customers are focused on improving Power, Performance and Area (PPA) parameters of their silicon. With the slowing of Moore’s Law on PPA improvements, these customers are redirecting their efforts into other aspects of chip design/manufacturing, opening up a wider variety of solutions from third parties.
Rapid data growth and customer demand for faster speeds, in and outside of the data center, is pushing the global data infrastructure industry to more widely adopt leading edge solutions more quickly to keep pace. This dynamic plus the success of open-source chip architecture RISC-V, has led to a substantive change in the industry, whereby companies are in-housing semiconductor design (auto, defense, hyperscalers, telecoms) creating specialized chips (ASICs) to differentiate their own products/services and create economies of scale given their increasing silicon consumption/product percentage. Meanwhile, the development of semiconductor IP is increasingly being outsourced, especially for complex niches like SerDes.
As such, in-housed design work is moving from internally developed components to high level integration activities similar to contractor/subcontractor work, essentially mixing/matching IP blocks from outside vendors and relying on design houses for specialized/difficult work. This style of design (integration) work is employed most aggressively with data infrastructure entities, as they require highly specialized silicon solutions in greater numbers than most other industries.
Chip complexity and higher costs are driving these customers to create/adopt chiplet designs, connection of multiple single process chips at various nodes to replicate a single, large, expensive System on a Chip (SoC). This increases the importance and content percentage of connectivity IP for a new design.
Customer contracts can vary widely on fees and royalties. License fees for IP blocks can be $2M-$5M while more integrated/complex connectivity IP or solutions can generate $15M-$20M per instance. These licenses can be for the technology or just the architecture. Fully designed chiplets integrating AWE IP can generate $30M-$50M in fees. Royalties can be $/unit and/or percent of ASP (2%-3% on the high end).
Customer cycles are typically 6-9 months of assessment, followed by up to 2 years of customer R&D to determine final design, followed by product launch with 5-10 years of life for a single product. Notably, data infrastructure hardware designs have a longer life span (5-10 years) than mobile/PC markets (2-3 years).
Revenue as per this cycle is as follows - NRE’s, license/support fees during a customer’s R&D period, followed by royalties and support fees once a product is manufactured and unit volumes ramp. The hardest part of the sales cycle is getting spec’d into a design, afterwards a long tail of royalties should be expected throughout the life of the final chip.
The engineering difficulty coupled with the need for performance differentiation results in connectivity IP garnering a premium in the market and strong demand from a wider range of customers, even the top semiconductor firms, as they focus on other elements of a chip.
As such, Alphawave should durably leverage their position to generate revenue/returns as customers have little choice if they require the highest speed solutions in the market. Additionally, products with long life spans in the data infrastructure market should bolster revenue levels for longer than most other IP firms tied to mobile or PC trends.
For OpenFive, an ASIC third-party design firm would be used if the customer is a non-semi company looking to simply subcontract out and integrate, or a semi company lacking a particular expertise/looking to double check design work. Data intensive customers, whose switches and other data transfer hardware may comprise 80%-90% wired connectivity IP may simply outsource the entire design to an AWE and focus on manufacturing and selling the product.
OpenFive’s agreement with SiFive to allow use of RISC-V IP is an additional benefit as customers are adopting this architecture for AI/ML workloads. Its open-source programming is also perfectly suited to heterogeneous chip integration via chiplets.
Third-party design firms are gaining share in the industry as time to market for new products pushes design teams to the limits and the cost of fixing a design error increases by a factor of 10 once the chip is on silicon and in production. Fully spec’d designs with the best-in-class connectivity IP should ease sale of IP, obtain greater wallet share in a chip program and speed time to market for customers.
Supplier Dynamics – SerDes a Niche in the Industry with Limited Supply of Engineers, Best Locations Canada/UK
Alphawave’s inputs and keys to performance are engineers with a specialty in analog and mixed-signal analysis/design. Throughout the semiconductor industry, analog disciplines (understanding physical phenomena and translating that to digital signal) amount to a small subset of practitioners, while most of the industry focus is on digital chips.
On top of that, SerDes, AWE’s core technology base, is increasingly niche by dealing with the physical layer on the silicon itself (PHY). This lack of supply is also another factor in why many customers outsource SerDes IP.
The company’s location in Canada/UK is partly driven by its proximity to the supply of these engineers from a few key universities as well as other semi IP firms. Not to mention AWE’s sourcing is more cost effective versus competing for engineers in Silicon Valley. Should demand increase for said engineering disciplines, the cycle time is at minimum 4-5 years for students to graduate university, and likely even longer as they require further training post-graduation.
For chip design, supply of engineers is more widespread, while niches in connectivity and RF exist.
Of the ~600 Alphawave employees, R&D engineers constitute over 85% of the total and ~300 design engineers are in India. Similarly, R&D comprises ~80% of AWE’s stock-based compensation.
Competitor Dynamics – Differentiated DSP-Platform and SerDes Focus Has Quickly Carved Out Leadership Position; Pro Forma OpenFive Entrenches IP into Designs, Fewer Large Rivals
SerDes is a difficult, highly niche domain with a limited supply of engineers and competitors. The wired connectivity IP market is ~70% outsourced as very few big firms develop their own IP.
The biggest companies in wired connectivity IP are Synopsys and Cadence followed by Rambus. Notably, SNPS and CDNS have wide ranging portfolios and are not focused on wired connectivity, while Rambus has what is considered trailing edge solutions in comparison to Alphawave and more focused on memory interface IP.
Importantly, the methods of traditional SerDes, utilizing purely analog techniques, limit the economic scalability of IP solutions as typically a wired connection IP would be created for an individual use case and would not be widely reusable. This results in a highly R&D capital intensive business lacking scale, of which only a few competitors allocate capital towards.
As transistor sizes have shrunk below 7nm, wired connections in and between chips exhibit increased EM interference and have become the limiting factor in data transfer. Compounding the issue, increasing transfer speeds also amplify signal integrity and power issues. Given these demands, SerDes solutions for the leading edge require mixed-signal technology, using digital signal processing to scale the data transfer stream at smaller nodes.
Most competitors are behind in their utilization of DSP, and/or lack the resources. With a ‘DSP chassis’ that allows for configurable wired solutions, Alphawave can not only maintain its advantage but also generate economics superior to competitors. Further, DSP-based connectivity allows for faster time to market for AWE’s customers.
Notably, Credo Technologies, a recent US SerDes IPO with very similar dynamics/markets/IP to AWE, only has solutions down to 7nm coupled with inferior margins.
By virtue of this DSP structure Alphawave was the first mover at the 112G rate (with design wins at the 5, 4, 3nm transistor nodes), jumping ahead of Synopsys, the previous leader, and Cadence. With most of the top semiconductor companies and a handful of the biggest hyperscalers as customers all scaling down to 3nm with speeds based on 224G (likely optical), AWE is in a leadership position to grab additional market share with a DSP chassis that can adapt solutions faster than competitors.
In the ASIC design market, OpenFive competes with a few other outsourced design firms, though differentiation comes down to specific skill set and focus. For OpenFive, their specialty included chip designs for networking and data transfer leveraging connectivity IP and RISC-V architectures via agreements with former parent company SiFive.
By combining AWE and OpenFive, the company can better defend its leading connectivity IP by integrating it into ASIC designs, a capability few IP firms have implemented. This move amounts to a vertical integration and gives AWE an ability to carve out a bigger portion of the custom silicon design market, while making their IP more accessible. Competitors in this realm include Broadcom, Marvell and MicroSemi, who implement similar strategies in the same markets.
Notably, this AWE/OpenFive combination is a divergence from an ARM-esque IP-only firm, but very necessary given the expansion of new chip architectures and data infrastructure end customers desire for custom solutions. Since SoftBank’s purchase of ARM, the company’s push into data centers has not created much traction or profits and is a proof point that attacking these markets with just IP tied to a single architecture is not a winning proposition.
Market Trends – Spread of High-Speed Connection Points in Data Center, 5G Infrastructure and Chiplet IC Design Should Drive Rapid Market Expansion
Wired Connectivity IP
The number of IP blocks per chip has increased from ~100 in ’12 to almost 200 in ’21. The market for semi IP is roughly $6B-$7B, ARM comprising ~40% share followed by SNPS at ~20%, CDNS at ~6% and AWE at 3%-5%. The connectivity IP market is ~25% of total IP, of which ~70% is outsourced, and is expected to grow ~14% per annum through ’24.
Data center capital spending is expected to grow ~13% per annum to ~$375B by ’26 according to Dell’Oro Group. The physical number of data centers is expected to increase ~4% per annum from ~1,700 in ’22 to ~2,100 by ’27.
SerDes connection points in a data center at the 100/200 Gbps level is expected to grow from several million points today to ~250 million points by ’25. SerDes Connection points at the 400/800 Gbps level are expected to grow from several million points today to ~35 million points by ’25, according to 650 Group. A helpful illustration of the potential connection points in the data center are shown below.
Source: Alphawave IP.
Importantly, within the data center RISC-V appears to be gaining adoption for AI/ML workloads. Deloitte expects RISC-V to be a ~$1B market in ’24. Approximately 70% of workloads in the data center run off Intel’s x86 architecture, down from almost 90% just a few years ago as AMD and others take share. Semico Research believes that RISC-V architectures could be in 20+ billion chips by ’27, up from today’s billion or so.
5G connection points are expected to grow over 30% per annum from ~1.7 billion in ’22 to ~4.5 billion by ’25, according to IDC. Mid and back-haul portions of the 5G infrastructure market, which would be serviced by wired connectivity solutions are expected to grow similarly. Overall spending towards 5G infrastructure is expected to increase from ~$12B in ’21 to ~$115B in ’26 according to Market Research Future.
AI server growth is expected to increase from ~$20B in ’22 to over $30B in ’25 according to IDC.
Custom Silicon Design
Custom silicon market is expected to increase from ~$5B in ’22 to over $20B in ’24 according to IDC.
Increasing chip complexity and cost started in earnest at the 28nm node, where cost per 100M transistor gates stood at $1.30, and escalated up to $1.52/100M transistors at the 5nm node. Overall manufacturing costs increased 4x from 45nm to 7nm nodes, while SoCs utilizing those nodes have gotten even larger creating yield issues at the wafer level.
Chiplets attempt to lower costs by having different components of a SoC at varying technology nodes and connecting them together. For example, a chiplet might have 5nm CPU cores connected to 22nm I/O with a high-speed interconnect.
For a SoC, wired connection points may be only one IP block from the package to the server. With chiplets, every component in the package would have its own interconnect and IP block, increasing the connectivity IP blocks by factors of 5 or more depending on the design. An illustration of the expansion of connection points within a SoC vs chiplet are shown below.